AD9942

Rev. A | Page 25 of 36

Table 20. Channel A and Channel B HBLK Individual Sequence Parameters

Parameter

Length

(Bit)

Range

Description

HBLKMASK

1

High/low

Masking polarity for H1 for Sequences 0 to 3 (0 = low; 1 = high).

Toggle Position 1

12

0 to 4095 pixel locations

First toggle position within the line for Sequences 0 to 3.

Toggle Position 2

12

0 to 4095 pixel locations

Second toggle position within the line for Sequences 0 to 3.

Toggle Position 3

12

0 to 4095 pixel locations

Third toggle position within the line for Sequences 0 to 3.

Toggle Position 4

12

0 to 4095 pixel locations

Fourth toggle position within the line for Sequences 0 to 3.

Toggle Position 5

12

0 to 4095 pixel locations

Fifth toggle position within the line for Sequences 0 to 3.

Toggle Position 6

12

0 to 4095 pixel locations

Sixth toggle position within the line for Sequences 0 to 3.

Table 21. Channel A and Channel B Horizontal Sequence Control Registers for CLPOB, PBLK, and HBLK

Register

Length

(Bit)

Range

Description

SCP

12

0 to 4095 line numbers

CLPOB/PBLK/HBLK SCP to define Horizontal Regions 0 to 3.

SPTR

2

0 to 3 sequence numbers

Sequence pointer for Horizontal Regions 0 to 3.

Table 22. Channel A and Channel B External HBLK Register Parameters

Register

Length (Bit)

Range

Description

HBLKDIR

1

High/low

Specifies HBLK internally generated or externally supplied. 0 = internal; 1 = external.

HBLKPOL

1

High/low

External HBLK active polarity. 0 = active low; 1 = active high.

HBLKEXTMASK

1

High/low

External HBLK masking polarity. 0 = mask H1 low; 1 = mask H1 high.

H-COUNTER SYNCHRONIZATION

The H-counter reset occurs seven CLI cycles after the HD falling edge.

0123

4567

89

10

11

12

14

15

012

3

H-COUNTER

RESET

VD_X

NOTES

1. INTERNAL H COUNTER IS RESET SEVEN CLI_X CYCLES AFTER THE HD_X FALLING EDGE (WHEN USING VDHDEDGE = 0).

2. TYPICAL TIMING RELATIONSHIP: CLI_X RISING EDGE IS COINCIDENT WITH HD_X FALLING EDGE.

HD_X

CLI_X

XX

XX

X

X

X

H COUNTER

(PIXEL COUNTER)

XX

X

Figure 26. H-Counter Synchronization