MC68340 datasheet(141/441 Pages) FREESCALE

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5- 4

MC68340 USER’S MANUAL

MOTOROLA

condition and count are checked after each execution of the data operations of the looped

instruction. The CPU32 automatically exits the loop mode on interrupts or other

exceptions.

5.1.4 Vector Base Register

The vector base register (VBR) contains the base address of the 1024-byte exception

vector table, which consists of 256 exception vectors. Exception vectors contain the

memory addresses of routines that begin execution at the completion of exception

processing. These routines perform a series of operations appropriate for the

corresponding exceptions. Because the exception vectors contain memory addresses,

each consists of one long word, except for the reset vector. The reset vector consists of

two long words: the address used to initialize the supervisor stack pointer (SSP) and the

address used to initialize the PC.

The address of an interrupt exception vector is derived from an 8-bit vector number and

the VBR. The vector numbers for some exceptions are obtained from an external device;

other numbers are supplied automatically by the processor. The processor multiplies the

vector number by 4 to calculate the vector offset, which is added to the VBR. The sum is

the memory address of the vector. All exception vectors are located in supervisor data

space, except the reset vector, which is located in supervisor program space. Only the

initial reset vector is fixed in the processor's memory map; once initialization is complete,

there are no fixed assignments. Since the VBR provides the base address of the vector

table, the vector table can be located anywhere in memory; it can even be dynamically

relocated for each task that is executed by an operating system. Refer to 5.5 Exception

Processing for additional details.

VECTOR BASE REGISTER (VBR)

5.1.5 Exception Handling

The processing of an exception occurs in four steps, with variations for different exception

causes. During the first step, a temporary internal copy of the status register (SR) is made,

and the SR is set for exception processing. During the second step, the exception vector

is determined. During the third step, the current processor context is saved. During the

fourth step, a new context is obtained, and the processor then proceeds with instruction

processing.

Exception processing saves the most volatile portion of the current context by pushing it

on the supervisor stack. This context is organized in a format called the exception stack

frame. This information always includes the SR and PC context of the processor when the

exception occurred. To support generic handlers, the processor places the vector offset in

the exception stack frame. The processor also marks the frame with a frame format. The

format field allows the return-from-exception (RTE) instruction to identify what information

is on the stack so that it may be properly restored.

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