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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC850 датащи(PDF) 12 Page - Freescale Semiconductor, Inc |
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MPC850 датащи(HTML) 12 Page - Freescale Semiconductor, Inc |
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12 / 72 page  MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 12 Freescale Semiconductor Bus Signal Timing B9 CLKOUT to A[6–31] RD/WR, BURST, D[0–31], DP[0–3], TSIZ[0–1], REG, RSV, AT[0–3], PTR high-Z 5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns B11 CLKOUT to TS, BB assertion 5.00 11.00 7.58 13.58 6.25 12.25 0.250 50.00 ns B11a CLKOUT to TA, BI assertion, (When driven by the memory controller or PCMCIA interface) 2.50 9.25 2.50 9.25 2.50 9.25 — 50.00 ns B12 CLKOUT to TS, BB negation 5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns B12a CLKOUT to TA, BI negation (when driven by the memory controller or PCMCIA interface) 2.50 11.00 2.50 11.00 2.50 11.00 — 50.00 ns B13 CLKOUT to TS, BB high-Z 5.00 19.00 7.58 21.58 6.25 20.25 0.250 50.00 ns B13a CLKOUT to TA, BI high-Z, (when driven by the memory controller or PCMCIA interface) 2.50 15.00 2.50 15.00 2.50 15.00 — 50.00 ns B14 CLKOUT to TEA assertion 2.50 10.00 2.50 10.00 2.50 10.00 — 50.00 ns B15 CLKOUT to TEA high-Z 2.50 15.00 2.50 15.00 2.50 15.00 — 50.00 ns B16 TA, BI valid to CLKOUT(setup time) 5 9.75 — 9.75 — 9.75 — — 50.00 ns B16a TEA, KR, RETRY, valid to CLKOUT (setup time) 5 10.00 — 10.00 — 10.00 — — 50.00 ns B16b BB, BG, BR valid to CLKOUT (setup time) 6 8.50 — 8.50 — 8.50 — — 50.00 ns B17 CLKOUT to TA, TEA, BI, BB, BG, BR valid (Hold time).5 1.00 — 1.00 — 1.00 — — 50.00 ns B17a CLKOUT to KR, RETRY, except TEA valid (hold time) 2.00 — 2.00 — 2.00 — — 50.00 ns B18 D[0–31], DP[0–3] valid to CLKOUT rising edge (setup time) 7 6.00 — 6.00 — 6.00 — — 50.00 ns B19 CLKOUT rising edge to D[0–31], DP[0–3] valid (hold time) 7 1.00 — 1.00 — 1.00 — — 50.00 ns B20 D[0–31], DP[0–3] valid to CLKOUT falling edge (setup time) 8 4.00 — 4.00 — 4.00 — — 50.00 ns B21 CLKOUT falling edge to D[0–31], DP[0–3] valid (hold time) 8 2.00 — 2.00 — 2.00 — — — — Table 6. Bus Operation Timing 1 (continued) Num Characteristic 50 MHz 66 MHz 80 MHz FFACT Cap Load (default 50 pF) Unit Min Max Min Max Min Max |
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