MPC850 datasheet(6/72 Pages) FREESCALE

6 / 72 page

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Features

•

QUICC multichannel controller (QMC) microcode features

— Up to 64 independent communication channels on a single SCC

— Arbitrary mapping of 0–31 channels to any of 0–31 TDM time slots

— Supports either transparent or HDLC protocols for each channel

— Independent TxBDs/Rx and event/interrupt reporting for each channel

•

One universal serial bus controller (USB)

— Supports host controller and slave modes at 1.5 Mbps and 12 Mbps

•

Two serial management controllers (SMCs)

— UART

— Transparent

— General circuit interface (GCI) controller

— Can be connected to the time-division-multiplexed (TDM) channel

•

One serial peripheral interface (SPI)

— Supports master and slave modes

— Supports multimaster operation on the same bus

•

One I2C® (interprocessor-integrated circuit) port

— Supports master and slave modes

— Supports multimaster environment

•

Time slot assigner

— Allows SCCs and SMCs to run in multiplexed operation

— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user-defined

— 1- or 8-bit resolution

— Allows independent transmit and receive routing, frame syncs, clocking

— Allows dynamic changes

— Can be internally connected to four serial channels (two SCCs and two SMCs)

•

Low-power support

— Full high: all units fully powered at high clock frequency

— Full low: all units fully powered at low clock frequency

— Doze: core functional units disabled except time base, decrementer, PLL, memory controller,

real-time clock, and CPM in low-power standby

— Sleep: all units disabled except real-time clock and periodic interrupt timer. PLL is active for

fast wake-up

— Deep sleep: all units disabled including PLL, except the real-time clock and periodic interrupt

timer

— Low-power stop: to provide lower power dissipation

MPC850 датащи(PDF) 6 Page - Freescale Semiconductor, Inc

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