MPC7448 datasheet(42/60 Pages) FREESCALE

42 / 60 page

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 3

Freescale Semiconductor

System Design Information

Table 15 summarizes the signal impedance results. The impedance increases with junction temperature

and is relatively unaffected by bus voltage.

9.5

Pull-Up/Pull-Down Resistor Requirements

The MPC7448 requires high-resistive (weak: 4.7-K

Ω) pull-up resistors on several control pins of the bus

interface to maintain the control signals in the negated state after they have been actively negated and

released by the MPC7448 or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1.

Some pins designated as being factory test pins must be pulled up to OVDD or down to GND to ensure

proper device operation. The pins that must be pulled up to OVDD are LSSD_MODE and TEST[0:3]; the

pins that must be pulled down to GND are L1_TSTCLK and TEST[4]. The CKSTP_IN signal should

likewise be pulled up through a pull-up resistor (weak or stronger: 4.7–1 K

Ω) to prevent erroneous

assertions of this signal.

In addition, the MPC7448 has one open-drain style output that requires a pull-up resistor (weak or

stronger: 4.7–1 K

Ω) if it is used by the system. This pin is CKSTP_OUT.

BVSEL0 and BVSEL1 should not be allowed to float, and should be configured either via pull-up or

pull-down resistors or actively driven by external logic. If pull-down resistors are used to configure

BVSEL0 or BVSEL1, the resistors should be less than 250

Ω (see Table 11). Because PLL_CFG[0:5]

must remain stable during normal operation, strong pull-up and pull-down resistors (1 K

Ω or less) are

recommended to configure these signals in order to protect against erroneous switching due to ground

bounce, power supply noise, or noise coupling.

During inactive periods on the bus, the address and transfer attributes may not be driven by any master and

may, therefore, float in the high-impedance state for relatively long periods of time. Because the MPC7448

must continually monitor these signals for snooping, this float condition may cause excessive power draw

by the input receivers on the MPC7448 or by other receivers in the system. These signals can be pulled up

through weak (10-K

Ω) pull-up resistors by the system, address bus driven mode enabled (see the

MPC7450 RISC Microprocessor Family Users’ Manual for more information on this mode), or they may

be otherwise driven by the system during inactive periods of the bus to avoid this additional power draw.

Preliminary studies have shown the additional power draw by the MPC7448 input receivers to be

negligible and, in any event, none of these measures are necessary for proper device operation. The

snooped address and transfer attribute inputs are: A[0:35], AP[0:4], TT[0:4], CI, WT, and GBL.

If address or data parity is not used by the system, and respective parity checking is disabled through HID1,

the input receivers for those pins are disabled and do not require pull-up resistors, therefore they may be

left unconnected by the system. If extended addressing is not used (HID0[XAEN] = 0), A[0:3] are unused

and must be pulled low to GND through weak pull-down resistors; additionally, if address parity checking

is enabled (HID1[EBA] = 1) and extended addressing is not used, AP[0] must be pulled up to OVDD

through a weak pull-up resistor. If the MPC7448 is in 60x bus mode, DTI[0:3] must be pulled low to GND

through weak pull-down resistors.

Table 15. Impedance Characteristics

At recommended operating conditions. See Table 4

Impedance

Processor Bus

Unit

Typical

33–42

Maximum

31–51

MPC7448 датащи(PDF) 42 Page - Freescale Semiconductor, Inc

MPC7448 датащи(HTML) 42 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

датащи скачать

ссылки URL