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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ICS9LPRS355 датащи(PDF) 24 Page - Renesas Technology Corp |
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ICS9LPRS355 датащи(HTML) 24 Page - Renesas Technology Corp |
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24 / 28 page  24 ICS9LPRS355 Datasheet 1205—06/24/14 Test Clarification Table Comments FSLC/ TEST_SEL HW PIN FSLB/ TEST_MODE HW PIN TEST ENTRY BIT B9b3 REF/N or HI-Z B9b4 OUTPUT <2.0V X 0 0 NORMAL >2.0V 0 X 0 HI-Z >2.0V 0 X 1 REF/N >2.0V 1 X 0 REF/N >2.0V 1 X 1 REF/N <2.0V X 1 0 HI-Z <2.0V X 1 1 REF/N HW SW Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FSLC./TEST_SEL -->3-level latched input If power-up w/ V>2.0V then use TEST_SEL If power-up w/ V<2.0V then use FSLC FSLB/TEST_MODE -->low Vth input TEST_MODE is a real time input If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through B9b3. If test mode is invoked by B9b3, only B9b4 is used to select HI-Z or REF/N FSLB/TEST_Mode pin is not used. Cycle power to disable test mode, one shot control B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) B9b4: 1= REF/N, Default = 0 (HI-Z) |
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