15

ICS9LPRS355

Datasheet

1205—06/24/14

Electrical Characteristics - SMBus Interface

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

Notes

SMBus Voltage

V

DD

2.7

5.5

V

1

Low-level Output Voltage

V

OLSMB

@ I

PULLUP

0.4

V

1

Current sinking at

V

OLSMB = 0.4 V

I

PULLUP

SMB Data Pin

4

mA

1

SCLK/SDATA

Clock/Data Rise Time

T

RI2C

(Max VIL - 0.15) to

(Min VIH + 0.15)

1000

ns

1

SCLK/SDATA

Clock/Data Fall Time

T

FI2C

(Min VIH + 0.15) to

(Max VIL - 0.15)

300

ns

1

Maximum SMBus Operating

Frequency

F

SMBUS

Block Mode

100

kHz

1

Electrical Characteristics - REF-14.318MHz

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

Notes

Long Accuracy

ppm

see Tperiod min-max values

-300

300

ppm

1,2

Clock period

T

period

14.318MHz output nominal

69.8203

69.8622

ns

2

Absolute min/max period

T

abs

14.318MHz output nominal

69.8203

70.86224

ns

2

Output High Voltage

V

OH

I

OH = -1 mA

2.4

V

1

Output Low Voltage

V

OL

I

OL = 1 mA

0.4

V

1

Output High Current

I

OH

V

OH @MIN = 1.0 V,

V

OH@MAX = 3.135 V

-33

-33

mA

1

Output Low Current

I

OL

V

OL @MIN = 1.95 V,

V

OL @MAX = 0.4 V

30

38

mA

1

Rising Edge Slew Rate

t

SLR

Measured from 0.8 to 2.0 V

1

4

V/ns

1

Falling Edge Slew Rate

t

FLR

Measured from 2.0 to 0.8 V

1

4

V/ns

1

Duty Cycle

d

t1

V

T = 1.5 V

45

55

%

1

Jitter

t

jcyc-c yc

V

T = 1.5 V

1000

ps

1

Notes on Electrical Characteristics:

1Guaranteed by design and characterization, not 100% tested in production.

2 Slew rate measured through Vswing centered around differential zero

3 Vxabs is defined as the voltage where CLK = CLK#

4 Only applies to the differential rising edge (CLK rising and CLK# falling)

6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz

5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK

and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#.

7 Operation under these conditions is neither implied, nor guaranteed.

9 See PCI Clock-to-Clock Delay Figure

8 Maximum input voltage is not to exceed maximum VDD