11

ICS9LPRS355

Datasheet

1205—06/24/14

REF

CPU(1:0)

CPU PLL1

SS

OSC

REF

SRC(11-9,4:3, 7:6)

PLL2

Non-SS

PLL3

SS

7

SRC8/CPU_ITP

PCIF5 (4:0)

SRC2/SATA

27MHz/SRC1/SE(2:1)

SE Outputs

SATA

DOT96MHz

PCI33MHz

SRC

SRC

SR C _M A IN

PCI33MHz

Differential Output

SRC0/DOT96

48MHz

48MHz

CPU

FSLA

CKPWRGD/PD#

PCI_STOP#

CPU_STOP#

CR#_(A:H)

27_Select

TME, ITP_EN

FSLC/TESTSEL

FSLB/TESTMODE

Control

Logic

X1

X2

27MHz_NonSS

ICS9LPRS355 follows Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for next

generation P4 Intel processors and Intel chipsets. ICS9LPRS355 is driven with a 14.318MHz crystal. It also provides a tight

ppm accuracy output for Serial ATA and PCI-Express support.

General Description

Block Diagram

Power Groups

VDD

GND

49

52

CPUCLK

Low power outputs

55

52

26, 36, 45

23, 29, 42

Low power outputs

39

23, 29, 42

PLL 1

20

19

Low power outputs

16

19

PLL 3

12

11

DOT 96Mhz

Low power outputs

911

61

58

28

PCICLK

SRCCLK

Pin Number

Description

PLL3/SE

Master Clock, Analog

USB 48

Xtal, REF