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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS5920 датащи(PDF) 149 Page - Applied Micro Circuits Corporation |
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CS5920 датащи(HTML) 149 Page - Applied Micro Circuits Corporation |
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149 / 160 page  S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 149 Data Book Table 6 summarizes the A. C. characteristics for the Add-On bus signals as they apply to the S5920. The figures after Table 6 visually indicate the timing relationships. Table 64. Add-On Timings, Functional Operation Range (VCC = 5.0 V ± 5%, 0°C to 7 0°C, 50 pF load on outputs for MAX, 0 pF load for MIN) Symbol Parameter Min Max Units Notes TACL ADCLK Cycle Time 25 ns t10 ADCLK High Time 10 ns t11 ADCLK Low Time 10 ns t12 ADCLK Rise Time (0.8V to 2.0V) 2.5 ns t13 ADCLK Fall Time (2.0V to 0.8V) 2.5 ns t14 PCICLK to BPCLK Delay, Rising 5.3 ns t15 PCICLK to BPCLK Delay, Falling 6.2 ns t16 PTADR# Low to DQ[31:0] Output Valid 13.1 ns 1 t17a PTADR# High to DQ[31:0] Output Hold 2 ns 1 t17b PTADR# High to DQ[31:0] Output Float 11.9 ns 1 t18 PTATN# Valid from ADCLK Rising Edge 13.5 ns t19 PTATN# Hold from ADCLK Rising Edge 4 ns t20 PTBURST# Valid from ADCLK Rising Edge 13 ns t21 PTBURST# Hold from ADCLK Rising Edge 4 ns t22 PTNUM[1:0] Valid from ADCLK Rising Edge 14.4 ns t23 PTNUM[1:0] Hold from ADCLK Rising Edge 4 ns t24 PTWR Valid from ADCLK Rising Edge 13.1 ns t25 PTWR Hold from ADCLK Rising Edge 4 ns t26 PTBE[3:0]# Valid from ADCLK Rising Edge 14.4 ns t27 PTBE[3:0]#Hold from ADCLK Rising Edge 3 ns t28 PTWAIT# Setup to ADCLK Rising Edge 11 ns t29 PTWAIT# Hold from ADCLK Rising Edge 1 ns t30 SELECT# Setup to ADCLK Rising Edge 8.9 ns t31 SELECT# Hold from ADCLK Rising Edge 1 ns t32 ADR[6:2] Setup to ADCLK Rising Edge 9.3 ns t33 ADR[6:2] Hold from ADCLK Rising Edge 1 ns |
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