CS5920 datasheet(99/160 Pages) AMCC

99 / 160 page

S5920 – PCI Product

Revision 1.01 – November 28, 2005

AMCC Confidential and Proprietary

DS1596

Data Book

PCI WRITE TRANSFERS

Write transfers on the PCI bus are one clock period

shorter than read transfers. This is because the

AD[31:0] bus does not require a turn-around cycle

between the address and data phases.

Write accesses to the S5920 operation registers are

shown in Figure 3. Here, the S5920 asserts the signal

STOP# in clock period 3. STOP# is asserted because

the S5920 does not support burst writes to operation

registers. Wait states may be added by the initiator by

not asserting the signal IRDY# during clock 2 and

beyond. There is only one condition where writes to

S5920 internal registers do not return TRDY# (but do

assert STOP#). This is called a target-initiated termi-

nation or target disconnect. This occurs when a write

attempt is made to a full Pass-Thru FIFO. The asser-

tion of STOP# without the assertion of TRDY#

indicates that the initiator should retry the operation

later. The S5920 will sustain a burst as long as the

FIFO is not full.

Figure 46. Burst PCI Bus Read Attempt to S5920 Reg-

isters or Expansion ROM

Figure 47. Burst PCI Bus Write of S5920 Registers

Target-Initiated Termination

There are situations where the target may end a trans-

fer prematurely. This is called “target-initiated

termination.” Target termination falls into three catego-

ries: disconnect, retry, and target abort. Only the

disconnect termination completes a data transfer.

Target Disconnects

There are many situations where a target may discon-

nect. Slow responding targets may disconnect to

permit more efficient (faster) devices to be accessed

while they prepare for the next data phase. Or a target

may disconnect if it recognizes that the next data

phase in a burst transfer is out of its address range. A

target disconnects by asserting STOP#, TRDY#, and

DEVSEL# as shown in Figures 4a and 4b. The initiator

in Figure 4a responds to the disconnect condition by

deasserting FRAME# on the following clock but does

not complete the data transfer until IRDY# is asserted.

The timing diagram in Figure 4b also applies to the

S5920.

The S5920 performs a target disconnect if a burst

access is attempted to any of its PCI Operation/Con-

figuration Registers, or to the Expansion ROM.

FRAME#

AD[31:0]

C/BE[3:0]#

IRDY#

TRDY#

DEVSEL#

STOP#

12345

PCLK

Address

Data

Bus Cmd

Byte Enables

(I)

(T)

(I) Driven by Initiator

(T) Driven by Target

FRAME#

AD[31:0]

C/BE[3:0]#

IRDY#

TRDY#

DEVSEL#

STOP#

PCLK

Address

Data 1

Bus

Cmd

BE 1

(I)

(T)

(I) Driven by Initiator

(T) Driven by Target

Data 2

BE 2

(I)

(T)

Data

Transfered

No Data

Transfered

CS5920 датащи(PDF) 99 Page - Applied Micro Circuits Corporation

CS5920 датащи(HTML) 99 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL