CS5920 datasheet(32/160 Pages) AMCC

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S5920 – PCI Product

Revision 1.01 – November 28, 2005

AMCC Confidential and Proprietary

DS1596

Data Book

USER ADD-ON BUS PIN DESCRIPTIONS

The following sets of signals represent the interface pins available for the Add-On bus. The following defines three

signal groups: S5920 register access signals, Pass-Thru channel signals, and general Add-On bus signals.

Table 18. Pass-Thru Data Channel Pins

Signal

Type

Description

PTMODE

Pass-Thru Mode. Configures the Pass-Thru data channel operation. High configures the S5920

in Passive mode allowing other devices to read/write data bus data. Low configures the S5920 in

Active mode. This mode allows the S5920 to actively drive signals and data onto the data bus.

This signal is connected to an internal pull-up.

PTATN#

out

Pass-Thru Attention. Signals a decoded PCI to Pass-Thru region bus cycle. PTATN# is gener-

ated to signal that Add-On logic Pass-Thru data must be read from or written to the S5920.

PTBURST#

out

Pass-Thru Burst. Informs the Add-On bus that the current Pass-Thru region decoded PCI bus

cycle is a burst access.

PTRDY#/

WAIT#

Pass-Thru Ready/Pass-Thru Wait. During passive mode, the signal is referred to as PTRDY#

and is asserted low to indicate Add-On logic has read/written data in response to a PTATN# sig-

nal. During active mode operation, the signal is referred to as WAIT# and can be driven low to

insert wait states or hold the S5920 from clocking data onto the data bus. PTRDY# or WAIT# is

synchronous to ADCLK.

PTNUM[1:0]

out

Pass-Thru Number. Identifies which of the four Pass-Thru regions the PTATN# read/write is

requesting. Only valid for the duration of PTATN# active. 00 = Base Address Register 1, 01 =

Base Address Register 2, 10 = Base Address Register 3, 11 = Base Address Register 4.

PTBE[3:0]#

out

Pass-Thru Byte Enables. During a PCI to Pass-Thru read, PTBE[3:0] indicate which bytes of a

DWORD are to be written into. During a PCI to Pass-Thru write, these pins indicate which bytes

of a DWORD are valid to read. PTBE[3:0]# are only valid while PTATN# is asserted.

PTADR#

t/s

Pass-Thru Address. Is an input when in passive mode. When asserted, the 32-bit Pass-Thru

address register contents are driven onto the DQ[31:0] bus. All other Add-On control signals

must be inactive during the assertion of PTADR# in passive mode. In active mode, becomes an

output and indicates a Pass-Thru address is on the DQ bus. The DQMODE signal does not

affect DQ bus width while the Pass-Thru address is driven.

PTWR

out

Pass-Thru Write. This signal indicates whether the current PCI to Pass-Thru bus transaction is a

read or write cycle. Valid only when PTATN# is active.

DXFER#

out

ACTIVE Transfer complete. When in ACTIVE mode, this output is asserted at the end of every 8-

16- or 32-bit data transfer cycle. This signal is not used in Passive mode.

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