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MPC604EC/D датащи(PDF) 9 Page - NXP Semiconductors

номер детали MPC604EC/D
подробное описание детали  PowerPC 604™ RISC Microprocessor Hardware Specifications
PDF  32 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
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MPC604EC/D датащи(HTML) 9 Page - NXP Semiconductors

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604 Hardware Specifications
9
Preliminary/Subject to Change without Notice
1.3.4 JTAG AC Timing Specifications
Table 8 provides the JTAG AC timing specifications.
Figure 5 provides the JTAG clock input timing diagram.
Figure 5. Clock Input Timing Diagram
Table 8. JTAG AC Timing Specifications (Independent of SYSCLK)
Num
Characteristic
Min
Max
Unit
Notes
TCK frequency of operation
0
16
MHz
1
TCK cycle time
62.5
—
ns
2
TCK clock pulse width measured at 1.5 V
25
—
ns
3
TCK rise and fall times
0
3
ns
4
TRST setup time to TCK rising edge
13
—
ns
2
5
TRST assert time
40
—
ns
6
Boundary-scan input data setup time
0
—
ns
7
Boundary-scan input data hold time
27
—
ns
8
TCK to output data valid
4
35
ns
9
TCK to output high impedance
3
24
ns
10
TMS, TDI data setup time
0
—
ns
11
TMS, TDI data hold time
25
—
ns
12
TCK to TDO data valid
4
24
ns
1
13
TCK to TDO high impedance
3
15
ns
1
Notes:
1. Load capacitance = 50 pF.
2. TRST is an asynchronous signal. The setup time is for test purposes.
TCK
VM
VM
1
2
2
3
3
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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