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604 Hardware Specifications

Preliminary/Subject to Change without Notice

1.7.2 PLL Power Supply Filtering

The AVDD power signal is provided on the 604 to provide power to the clock generation phase-lock loop.

To ensure stability of the internal clock, the power supplied to the AVDD input signal should be filtered

using a circuit similar to the one shown in Figure 16. Note that the capacitors should be placed as close as

possible to the AVDD input signal.

Figure 16. PLL Power Supply Filter Circuit

1.7.3 Decoupling Recommendations

The 604 can generate transient power surges and high frequency noise in its power supply, especially while

driving large capacitive loads. This noise must be prevented from reaching other components in the 604

system, and the 604 itself requires a clean, tightly regulated source of power. Therefore, it is strongly

recommended that the system designer place at least one decoupling capacitor with a low ESR (effective

series resistance) rating at each Vdd and OVdd pin of the 604.

These capacitors should range in value from 220 pF to 10

µF to provide both high- and low-frequency

filtering, and should be placed as close as possible to their associated Vdd pin. Surface-mount tantalum or

ceramic devices are preferred. It is also recommended that these decoupling capacitors receive their power

from Vdd and GND power planes in the PCB, utilizing short traces to minimize inductance in the traces.

Power and ground connections must be made to all external Vdd and GND pins of the 604.

1.7.4 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal

level. Unused active low inputs should be tied to Vdd. Unused active high inputs should be connected to

GND. All NC (no-connect) pins must remain unconnected.

VDD

AVDD

10 OHMS

10 uF

.1 uF

GND

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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