PowerPC 604 RISC Microprocessor Technical Summary

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The hashed page table is a variable-sized data structure that defines the mapping between virtual page

numbers and physical page numbers. The page table size is a power of 2, and its starting address is a multiple

of its size.

Address translations are enabled by setting bits in the MSR—MSR[IR] enables instruction address

translations and MSR[DR] enables data address translations.

The 604’s MMUs support up to 4 Petabytes (252) of virtual memory and 4 Gigabytes (232) of physical

memory. The MMUs support block address translations, I/O controller interface segments, and page

translation of memory segments. Referenced and changed status are maintained by the processor for each

page to assist implementation of a demand-paged virtual memory system.

Separate but identical translation logic is implemented for data accesses and for instruction accesses. The

604 implements two 128-entry, two-way set associative translation lookaside buffers (TLBs), one for

instructions and one for data. These TLBs can be accessed simultaneously.

1.2.4 Cache Implementation

The PowerPC architecture does not define hardware aspects of cache implementations. For example,

whereas the 604 implements separate data and instruction caches (Harvard architecture), other processors

may use a unified cache, or no cache at all. The PowerPC architecture defines the unit of coherency as a

cache block, which for the 604 is a 32-byte (eight-word) line.

PowerPC implementations can control the following memory access modes on a page or block basis:

•

Write-back/write-through mode

•

Cache-inhibited mode

•

Memory coherency

•

Guarded memory (prevents access for speculative execution)

1.2.4.1 Instruction Cache

The 604’s 16-Kbyte, four-way set associative instruction cache is physically indexed. Within a single cycle,

the instruction cache provides up to four instructions. Instruction cache coherency is not maintained by

hardware.

The PowerPC architecture defines a special set of instructions for managing the instruction cache. The

instruction cache can be invalidated entirely or on a cache-block basis. The instruction cache can be disabled

and invalidated by setting the HID0[16] and HID0[20] bits, respectively. The instruction cache can be

locked by setting HID0[18].

1.2.4.2 Data Cache

The 604’s data cache is a 16-Kbyte, four-way set associative cache. It is a physically-indexed, nonblocking,

write-back cache with hardware support for reloading on cache misses. Within one cycle, the data cache

provides double-word access to the LSU.

To ensure cache coherency, the 604 data cache supports the four-state MESI (modified/exclusive/shared/

invalid) protocol. The data cache tags are dual-ported, so the process of snooping does not affect other

transactions on the system interface. If a snoop hit occurs, the LSU is blocked internally for one cycle to

allow the eight-word block of data to be copied to the writeback buffer.

Like the instruction cache, the data cache can be invalidated all at once or on a per cache block basis. The

data cache can be disabled and invalidated by setting the HID0[17] and HID0[21] bits, respectively. The

data cache can be locked by setting HID0[19].

Freescale Semiconductor, Inc.

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