MPC604 datasheet(28/32 Pages) NXP

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PowerPC 604 RISC Microprocessor Technical Summary

External

interrupt

00500

An external interrupt occurs when the external exception signal, INT, is

asserted. This signal is expected to remain asserted until the exception handler

begins execution. Once the signal is detected, the 604 stops dispatching

instructions and waits for all dispatched instructions to complete. Any

exceptions associated with dispatched instructions are taken before the

interrupt is taken.

Alignment

00600

An alignment exception is caused when the processor cannot perform a

memory access for the following reasons:

A ﬂoating-point load, store, lmw, stmw, lwarx, or stwcx. instruction is not word-

aligned.

A dcbz instruction refers to a page that is marked either cache-inhibited or

write-through.

A dcbz instruction has executed when the 604 data cache is locked or disabled.

An access is not naturally aligned in little-endian mode.

An ecowx or eciwx is not word-aligned.

An lmw, stmw, lswi, lswx, stswi, or stswx is issued in little-endian mode.

Program

00700

A program exception is caused by one of the following exception conditions,

which correspond to bit settings in SRR1 and arise during execution of an

instruction:

•

Floating-point exceptions—A ﬂoating-point enabled exception condition

causes an exception when FPSCR[FEX] is set and depends on the values

in MSR[FE0] and MSR[FE1].

FPSCR[FEX] is set by the execution of a ﬂoating-point instruction that

causes an enabled exception or by the execution of a “move to FPSCR”

instruction that results in both an exception condition bit and its

corresponding enable bit being set in the FPSCR.

•

Illegal instruction—An illegal instruction program exception is generated

when execution of an instruction is attempted with an illegal opcode or illegal

combination of opcode and extended opcode ﬁelds or when execution of an

optional instruction not provided in the speciﬁc implementation is attempted

(these do not include those optional instructions that are treated as no-ops).

•

Privileged instruction—A privileged instruction type program exception is

generated when the execution of a privileged instruction is attempted and

the MSR register user privilege bit, MSR[PR], is set. This exception is also

generated for mtspr or mfspr with an invalid SPR ﬁeld if SPR[0] = 1 and

MSR[PR] = 1.

•

Trap—A trap type program exception is generated when any of the

conditions speciﬁed in a trap instruction is met.

Floating-point

unavailable

00800

A ﬂoating-point unavailable exception is caused by an attempt to execute a

ﬂoating-point instruction (including ﬂoating-point load, store, and move

instructions) when the ﬂoating-point available bit is disabled (MSR[FP] = 0).

Decrementer

00900

The decrementer exception occurs when the most signiﬁcant bit of the

decrementer (DEC) register transitions from 0 to 1.

Reserved

00A00–00BFF

—

System call

00C00

A system call exception occurs when a System Call (sc) instruction is executed.

Trace

00D00

Either the MSR[SE] = 1 and any instruction (except rﬁ) successfully completed

or MSR[BE] = 1 and a branch instruction is completed.

Table 3. Exceptions and Conditions (Continued)

Exception

Type

Vector Offset

(hex)

Causing Conditions

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

IVE

D B

Y F

INC

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