PowerPC 604 RISC Microprocessor Technical Summary

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— Eight condition register (CR) rename buffers

The 604 rename buffers are described in Section 1.2.1.5, “Rename Buffers”

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Completion unit

— The completion unit retires an instruction from the 16-entry reorder buffer when all instructions

ahead of it have been completed and the instruction has finished execution.

— Guarantees sequential programming model (precise exception model)

— Monitors all dispatched instructions and retires them in order

— Tracks unresolved branches and removes speculatively executed, dispatched, and fetched

instructions if branch is mispredicted

— Retires as many as four instructions per clock

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Separate on-chip instruction and data caches (Harvard architecture)

— 16-Kbyte, four-way set-associative instruction and data caches

— LRU replacement algorithm

— 32-byte (eight word) cache block size

— Physically indexed; physical tags. Note that the PowerPC architecture refers to physical address

space as real address space.

— Cache write-back or write-through operation programmable on a per page or per block basis

— Instruction cache can provide four instructions per clock; data cache can provide two words per

clock

— Caches can be disabled in software

— Caches can be locked

— Parity checking performed on both caches

— Data cache coherency (MESI) maintained in hardware

— Secondary data cache support provided

— Instruction cache coherency maintained in software

— Provides a no-DRTRY/data streaming mode, which allows consecutive burst read data transfers

to occur without intervening dead cycles. This mode also disables data retry operations.

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Separate memory management units (MMUs) for instructions and data

— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte

segment size

— Both TLBs are 128-entry and two-way set associative

— TLBs are hardware reloadable. That is, the page table search is performed in hardware.

— Separate IBATs and DBATs (four each) also defined as SPRs.

— Separate instruction and data translation lookaside buffers (TLBs)

— LRU replacement algorithm

— Hardware table search (caused by TLB misses) through hashed page tables

— 52-bit virtual address; 32-bit physical address

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Bus interface features include the following:

— Selectable processor-to-bus clock frequency ratios (1:1, 1.5:1, 2:1, and 3:1)

— A 64-bit split-transaction external data bus with burst transfers

Freescale Semiconductor, Inc.

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