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PowerPC 604 RISC Microprocessor Technical Summary

subdivision of the processor clock frequency. In the 604. the time base frequency is 1/4th of the bus

clock frequency (as is the decrementer frequency). Counting is enabled by the Time Base Enable

signal (TBE).

•

Block address translation (BAT) registers—The PowerPC architecture defines 16 BAT registers,

divided into four pairs of data BATs (DBATs) and four pairs of instruction BATs (IBATs).

The 604 includes the following registers not defined by the PowerPC architecture:

•

Instruction address breakpoint register (IABR)—This register can be used to cause a breakpoint

exception to occur if a specified instruction address is encountered.

•

Data address breakpoint register (DABR)—This register can be used to cause a breakpoint

exception to occur if a specified data address is encountered.

•

Hardware implementation-dependent register 0 (HID0)—This register is used to control various

functions within the 604, such as enabling checkstop conditions, and locking, enabling, and

invalidating the instruction and data caches.

•

Processor identification register (PIR)—The PIR is a supervisor-level register that has a right-

justified, four-bit field that holds a processor identification tag used to identify a particular 604. This

tag is used to identify the processor in multiple-master implementations.

•

Performance monitor counter registers (PMC1 and PMC2). The counters are used to record the

number of times a certain event has occurred.

•

Performance monitor control register (MMCR0)—This is used for enabling various performance

monitoring interrupt conditions and establishes the function of the counters.

•

Sampled instruction address and sampled data address registers (SIA and SDA)—These registers

hold the addresses for instruction and data used by the performance monitoring interrupt.

Note that while it is not guaranteed that the implementation of HID registers is consistent among PowerPC

processors, other processors may be implemented with similar or identical HID registers.

1.3.3 Instruction Set and Addressing Modes

The following subsections describe the PowerPC instruction set and addressing modes in general.

1.3.3.1 PowerPC Instruction Set and Addressing Modes

All PowerPC instructions are encoded as single-word (32-bit) opcodes. Instruction formats are consistent

among all instruction types, permitting efficient decoding to occur in parallel with operand accesses. This

fixed instruction length and consistent format greatly simplifies instruction pipelining.

1.3.3.1.1 Instruction Set

The 604 implements the entire PowerPC instruction set (for 32-bit implementations) and most optional

PowerPC instructions. The PowerPC instructions can be grouped into the following general categories:

•

Integer instructions—These include computational and logical instructions.

— Integer arithmetic instructions

— Integer compare instructions

— Logical instructions

— Integer rotate and shift instructions

•

Floating-point instructions—These include floating-point computational instructions, as well as

instructions that affect the FPSCR. Floating-point instructions include the following:

— Floating-point arithmetic instructions

Freescale Semiconductor, Inc.

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