PowerPC 604 RISC Microprocessor Technical Summary

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1.2.1.4 Completion Unit

The completion unit retires executed instructions from the reorder buffer (ROB) in the completion unit and

updates register files and control registers. The completion unit recognizes exception conditions and

discards any operations being performed on subsequent instructions in program order. The completion unit

can quickly remove instructions from a mispredicted branch, and the decode/dispatch unit begins

dispatching from the correct path.

The instruction is retired from the reorder buffer when it has finished execution and all instructions ahead

of it have been completed. The instruction’s result is written into the appropriate register file and is removed

from the rename buffers at or after completion. At completion, the 604 also updates any other resource

affected by this instruction. Several instructions can complete simultaneously. Most exception conditions

are recognized at completion time.

1.2.1.5 Rename Buffers

To avoid contention for a given register location, the 604 provides rename registers for storing instruction

results before the completion unit commits them to the architected register. Twelve rename registers are

provided for the GPRs, eight for the FPRs, and eight each for the condition register. GPRs are described in

Section 1.3.2.1, “General-Purpose Registers (GPRs),” FPRs are described in Section 1.3.2.2, “Floating-

Point Registers (FPRs),” and the condition register is described in Section 1.3.2.3, “Condition Register

(CR).”

When the dispatch unit dispatches an instruction to its execution unit, it allocates a rename register for the

results of that instruction. The dispatch unit also provides a tag to the execution unit identifying the result

that should be used as the operand. When the proper result is returned to the rename buffer it is latched into

the reservation station. When all operands are available in the reservation station, the execution can begin.

The completion unit does not transfer instruction results from the rename registers to the registers until any

speculative branch conditions preceding it in the completion queue are resolved and the instruction itself is

retired from the completion queue without exceptions. If a speculatively executed branch is found to have

been incorrectly predicted, the speculatively executed instructions following the branch are flushed from the

completion queue and the results of those instructions are flushed from the rename registers.

1.2.2 Execution Units

The following sections describe the 604’s arithmetic execution units—the two single-cycle IUs, the multiple

cycle IU, and the FPU. When the reservation station sees the proper result being written back, it will grab it directly

from one of the result buses. Once all operands are in the reservation station for an instruction, it is eligible to be

executed.

Reservation stations temporarily store dispatched instructions that cannot be executed until all of

the source operands are valid.

1.2.2.1 Integer Units (IUs)

The two single-cycle IUs (SCIUs) and one multiple-cycle IU (MCIU) execute all integer instructions. These

are shown in Figure 1 and Figure 2. Each IU has a dedicated result bus that connects to rename buffers and

to all reservation stations. Each IU has a two-entry reservation station to reduce stalls. The reservation

station can receive instructions from the decode/dispatch unit and operands from the GPRs, the rename

buffers, or the result buses.

Each SCIU consists of three single-cycle subunits—a fast adder/comparator, a subunit for logical

operations, and a subunit for performing rotates, shifts, and count-leading-zero operations. These subunits

handle all one-cycle arithmetic instructions; only one subunit can execute an instruction at a time.

Freescale Semiconductor, Inc.

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