AD7142 datasheet(32/68 Pages) AD

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AD7142

Rev. 0 | Page 32 of 68

SDI

SCLK

READBACK DATA FOR

STARTING REGISTER ADDRESS

1516

1718

910

XXX XXX XXX

XXX D15 D14

D15

D14

XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX

SDO

16-BIT COMMAND WORD

ENABLE WORD

R/W

NOTES

1. MULTIPLE REGISTERS CAN BE READ BACK CONTINUOUSLY.

2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.

3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD BEING READ BACK ON THE SDO PIN.

4. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.

5. X DENOTES DON’T CARE.

6. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.

7. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL READBACK OPERATION:

CW[15:11] = 11100 (ENABLE WORD)

CW[10] = 1 (R/W)

CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS)

READBACK DATA FOR

NEXT REGISTER ADDRESS

Figure 47. Sequential Register Readback SPI Timing

I2C COMPATIBLE INTERFACE

The AD7142-1 supports the industry standard 2-wire I2C serial

interface protocol. The two wires associated with the I2C timing are

the SCLK and the SDA inputs. The SDA is an I/O pin that allows

both register write and register readback operations. The AD7142-1

is always a slave device on the I2C serial interface bus.

It has a 7-bit device address, Address 0101 1XX. The lower two

bits are set by tying the ADD0 and ADD1 pins high or low. The

AD7142-1 responds when the master device sends its device

address over the bus. The AD7142-1 cannot initiate data

transfers on the bus.

Table 17. AD7142-1 I2C Device Address

ADD1

ADD0

I2C Address

0101 100

0101 101

0101 110

0101 111

Data Transfer

Data is transferred over the I2C serial interface in 8-bit bytes.

The master initiates a data transfer by establishing a start con-

dition, defined as a high-to-low transition on the serial data

line, SDA, while the serial clock line, SCLK, remains high. This

indicates that an address/data stream follows.

All slave peripherals connected to the serial bus respond to the

start condition and shift in the next eight bits, consisting of a

7-bit address (MSB first) plus an R/W bit that determines the

direction of the data transfer. The peripheral whose address

corresponds to the transmitted address responds by pulling the

data line low during the ninth clock pulse. This is known as the

acknowledge bit. All other devices on the bus now remain idle

while the selected device waits for data to be read from, or

written to it. If the R/W bit is a zero, the master writes to the

slave device. If the R/W bit is a one, the master reads from the

slave device.

Data is sent over the serial bus in a sequence of nine clock

pulses, eight bits of data followed by an acknowledge bit from

the slave device. Transitions on the data line must occur during

the low period of the clock signal and remain stable during the

high period, since a low-to-high transition when the clock is

high can be interpreted as a stop signal. The number of data

bytes transmitted over the serial bus in a single read or write

operation is limited only by what the master and slave devices

can handle.

When all data bytes are read or written, a stop condition is

established. A stop condition is defined by a low-to-high

transition on SDA while SCLK remains high. If the AD7142

encounters a stop condition, it returns to its idle condition, and

the address pointer register resets to Address 0x00.

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