AD7142 datasheet(25/68 Pages) AD

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AD7142

Rev. 0 | Page 25 of 68

INTERRUPT OUTPUT

The AD7142 has an interrupt output that triggers an interrupt

service routine on the host processor. The INT signal is on

Pin 25, and is an open-drain output. There are three types of

interrupt events on the AD7142: a CDC conversion complete

interrupt, a sensor threshold interrupt, and a GPIO interrupt.

Each interrupt has enable and status registers. The conversion

complete and sensor threshold interrupts can be enabled on a

per conversion stage basis. The status registers indicate what

type of interrupt triggered the INT pin. Status registers are

cleared, and the INT signal is reset high, during a read

operation. The signal returns high as soon as the read address

has been set up.

CDC CONVERSION COMPLETE INTERRUPT

The AD7142 interrupt signal asserts low to indicate the

completion of a conversion stage, and new conversion result

data is available in the registers.

The interrupt can be independently enabled for each conversion

stage. Each conversion stage complete interrupt can be enabled via

the STAGE_COMPLETE_EN register (Address 0x007). This

this bit to 1 enables the interrupt for that stage. Clearing this bit to 0

disables the conversion complete interrupt for that stage.

In normal operation, the AD7142’s interrupt is enabled only for the

last stage in a conversion sequence. For example, if there are five

conversion stages, the conversion complete interrupt for STAGE4 is

enabled. INT only asserts when all five conversion stages are

complete, and the host can read new data from all five result

registers. The interrupt is cleared by reading the

STAGE_COMPLETE_STATUS_INT register located at Address

0x00A.

stage. If a bit is set, it means that the conversion complete

interrupt for the corresponding stage was triggered. This

that triggered the interrupt has gone away.

SENSOR TOUCH INTERRUPT

The sensor touch interrupt mode is implemented when the host

processor requires an interrupt only when a sensor is contacted.

Configuring the AD7142 into this mode results in the interrupt

being asserted when the user makes contact with the sensor and

again when the user lifts off the sensor. The second interrupt is

required to alert the host processor that the user is no longer

contacting the sensor.

The registers located at Address 0x005 and Address 0x006 are

used to enable the interrupt output for each stage. The registers

located at Address 0x008 and Address 0x009 are used to read

back the interrupt status for each stage.

Figure 35 shows the interrupt output timing during contact with

one of the sensors connected to STAGE0 while operating in the

sensor touch interrupt mode. For a low limit configuration, the

interrupt output is asserted as soon as the sensor is contacted and

again after the user has stopped contacting the sensor.

Note: The interrupt output remains low until the host processor

reads back the interrupt status registers located at Address

0x008 and Address 0x009.

The interrupt output is asserted when there is a change in the

threshold status bits. This could indicate that a user is now

touching the sensor(s) for the first time, the number of sensors

being touched has changed, or the user is no longer touching

the sensor(s). Reading the status bits in the interrupt status

CONVERSION

STAGE

SERIAL

READ BACK

NOTES:

1. USER TOUCHING DOWN ON SENSOR

2. ADDRESS 0X008 READ BACKTO CLEAR INTERRUPT

3. USER LIFTING OFF OF SENSOR

4. ADDRESS 0X008 READ BACK TO CLEAR INTERRUPT

STAGE0

STAGE1

INT OUTPUT

Figure 35. Example of Sensor Touch Interrupt

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