AD7142 datasheet(38/68 Pages) AD

38 / 68 page

AD7142

Rev. 0 | Page 38 of 68

The AD7142 address space is divided into three different

57 illustrates the division of these three banks.

Bank 1 registers contain control registers, CDC conversion

control registers, interrupt enable registers, interrupt status

registers, CDC 16-bit conversion data registers, device ID

registers, and proximity status registers.

Bank 2 registers contain the configuration registers used for

uniquely configuring the CIN inputs for each conversion stage.

Initialize the Bank 2 configuration registers immediately after

power-up to obtain valid CDC conversion result data.

Bank 3 registers contain the results of each conversion stage.

These registers automatically update at the end of each conversion

sequence. Although these registers are primarily used by the

AD7142 internal data processing, they are accessible by the host

processor for additional external data processing, if desired.

Default values are undefined for Bank 2 registers and Bank 3

registers until after power up and configuration of the Bank 2

registers.

ADDR 0x000

ADDR 0x018

ADDR 0x001

ADDR 0x005

ADDR 0x008

ADDR 0x00B

ADDR 0x017

ADDR 0x7F0

SET UP CONTROL

(1 REGISTER)

CALIBRATION AND SET UP

(4 REGISTERS)

INTERRUPT ENABLE

(3 REGISTERS)

INTERRUPT STATUS

(3 REGISTERS)

CDC 16-BIT CONVERSION DATA

(12 REGISTERS)

DEVICE ID REGISTER

INVALID DO NOT ACCESS

ADDR 0x080

ADDR 0x0B8

ADDR 0x088

ADDR 0x090

ADDR 0x098

ADDR 0x0A0

ADDR 0x0A8

ADDR 0x0B0

ADDR 0x0C8

ADDR 0x0C0

STAGE 0 CONFIGURATION

(8 REGISTERS)

STAGE 1 CONFIGURATION

(8 REGISTERS)

STAGE 2 CONFIGURATION

(8 REGISTERS)

STAGE 3 CONFIGURATION

(8 REGISTERS)

STAGE 4 CONFIGURATION

(8 REGISTERS)

STAGE 5 CONFIGURATION

(8 REGISTERS)

STAGE 6 CONFIGURATION

(8 REGISTERS)

STAGE 7 CONFIGURATION

(8 REGISTERS)

STAGE 8 CONFIGURATION

(8 REGISTERS)

STAGE 9 CONFIGURATION

(8 REGISTERS)

STAGE 10 CONFIGURATION

(8 REGISTERS)

STAGE 11 CONFIGURATION

(8 REGISTERS)

ADDR 0x0D8

ADDR 0x0D0

ADDR 0x0E0

ADDR 0x0B8

ADDR 0x088

ADDR 0x090

ADDR 0x098

ADDR 0x0A0

ADDR 0x0A8

ADDR 0x0B0

ADDR 0x0C8

ADDR 0x0C0

STAGE 0 RESULTS

(36 REGISTERS)

ADDR 0x28F

ADDR 0x0D0

STAGE 1 RESULTS

(36 REGISTERS)

STAGE 10 RESULTS

(36 REGISTERS)

STAGE 9 RESULTS

(36 REGISTERS)

STAGE 8 RESULTS

(36 REGISTERS)

STAGE 7 RESULTS

(36 REGISTERS)

STAGE 6 RESULTS

(36 REGISTERS)

STAGE 5 RESULTS

(36 REGISTERS)

STAGE 4 RESULTS

(36 REGISTERS)

STAGE 3 RESULTS

(36 REGISTERS)

STAGE 2 RESULTS

(36 REGISTERS)

STAGE 11 RESULTS

(36 REGISTERS)

PROXIMITY STATUS REGISTER

ADDR 0x042

INVALID DO NOT ACCESS

ADDR 0x043

Figure 57. Layout of Bank 1 Registers, Bank 2 Registers, and Bank 3 Registers

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