AD7142 datasheet(43/68 Pages) AD

43 / 68 page

AD7142

Rev. 0 | Page 43 of 68

Address

Data Bit

Default

Value

Type

Name

Description

[4]

STAGE4_HIGH_INT_EN

STAGE4 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high threshold is exceeded

[5]

STAGE5_HIGH_INT_EN

STAGE5 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high threshold is exceeded

[6]

STAGE6_HIGH_INT_EN

STAGE6 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high threshold is exceeded

[7]

STAGE7_HIGH_INT_EN

STAGE7 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high threshold is exceeded

[8]

STAGE8_HIGH_INT_EN

STAGE8 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high threshold is exceeded

[9]

STAGE9_HIGH_INT_EN

STAGE9 sensor interrupt low limit control

0 = interrupt source disabled

1 = INT asserted if STAGE10_LOW is exceeded

[10]

STAGE10_HIGH_INT_EN

STAGE10 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high threshold is exceeded

[11]

STAGE11_HIGH_INT_EN

STAGE11 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high threshold is exceeded

[15:12]

Unused

Set unused register bits = 0

Table 26. STAGE_COMPLETE_INT_EN Register

Address

Data Bit

Default

Value

Type

Name

Description

0x007

[0]

R/W

STAGE0_COMPLETE_EN

STAGE0 conversion interrupt control

0 = interrupt source disabled

1 = INT asserted at completion of STAGE0 conversion

[1]

STAGE1_COMPLETE_EN

STAGE1 conversion interrupt control

0 = interrupt source disabled

1 = INT asserted at completion of STAGE1 conversion

[2]

STAGE2_COMPLETE_EN

STAGE2 conversion interrupt control

0 = interrupt source disabled

1 = INT asserted at completion of STAGE2 conversion

[3]

STAGE3_COMPLETE_EN

STAGE3 conversion interrupt control

0 = interrupt source disabled

1 = INT asserted at completion of STAGE3 conversion

[4]

STAGE4_COMPLETE_EN

STAGE4 conversion interrupt control

0 = interrupt source disabled

1 = INT asserted at completion of STAGE4 conversion

[5]

STAGE5_COMPLETE_EN

STAGE5 conversion interrupt control

0 = interrupt source disabled

1 = INT asserted at completion of STAGE5 conversion

[6]

STAGE6_COMPLETE_EN

STAGE6 conversion interrupt control

0 = interrupt source disabled

1 = INT asserted at completion of STAGE6 conversion

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