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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STUW81300 датащи(PDF) 37 Page - STMicroelectronics |
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STUW81300 датащи(HTML) 37 Page - STMicroelectronics |
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37 / 63 page  DS11314 Rev 7 37/63 STuW81300 Circuit description 58 ST1 Register Address: STuW81300BaseAddress + 0x01 Type: R/W Applicability: Double buffered (based upon DBR bit setting) Description: FRAC value, RF1 output control 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7654 321 0 RW RW RW RW RW RW RW [26] DBR: double buffering bit enable 1: the register is buffered and transferred only once the master register ST0 is written [25] RESERVED: must be set to ‘0’ [24] RF1_OUT_PD: RF1 output power down 0: RF1 output enabled 1: RF1 output disabled [23] MAN_CALB_EN: enables manual VCO calibrator mode 0: automatic VCO calibration (VCO_SEL, VCO_WORD settings are ignored) 1: manual VCO calibration (VCO_SEL, VCO_WORD settings are used; VCO calibration procedure is inhibited; VCO_SEL and VCO_WORD bit to be set in ST6 Register) [22] PLL_ SEL: selection of the signal path to PLL 0: VCO direct to PLL 1: VCO divided by 2 to PLL (mandatory for VCO freq > 6 GHz; in such a case the overall N value is doubled and NINT,FRAC and MOD must be updated accordingly at the half value) [21] RF1_ SEL: RF1 output divider selection 0: VCO direct 1: VCO divided by 2 [20:0] FRAC: Fractional value bit; set the numerator value of the fractional part of the overall division ratio (N=NINT+FRAC/MOD) Range: 0 to 2097151 (must be < MOD) |
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