STUW81300 datasheet(29/63 Pages) STMICROELECTRONICS

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DS11314 Rev 7

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STuW81300

Circuit description

7.9

Cycle slip reduction

The use of high FPFD/PLL_BW ratios may lead to an increased settling time due to cycle

slips.

A cycle slip compensation circuit is provided which automatically increases the charge

pump current for high-frequency errors and restores the programmed value at the end of the

locking phase.

7.10

Voltage controlled oscillators (VCOs)

The STuW81300 employs four low-noise VCOs with monolithic LC tanks to cover a

frequency range from 3850 MHz to 8000 MHz. Combined with an on-chip frequency doubler

and divide-by-two stage, the VCOs allow synthesis of any frequency across the 1.925 GHz

to 16 GHz range.

Each VCO is implemented using a structure with multiple sub-bands to maintain a low VCO

sensitivity (KVCO), resulting in low phase noise and low spurs performance.

The correct VCO and sub-band selection is automatically performed by dedicated digital

circuitry (clocked by the PFD) every time a new frequency is programmed. The VCO auto-

calibration procedure is activated once the ST0 Register is updated.

During the selection procedure the VCTRL of the VCO is charged to a fixed reference

voltage. A stable reference clock signal to the device must present before the VCO

calibration begins. The procedure for the VCO and sub-band selection takes approximately

13 CALBCLK cycles.

The calibrator clock frequency is linked to PFD frequency (CALBCLK = FPFD/CALDIV) and

should be adjusted in order to achieve correct operations. The maximum allowed frequency

is 250 kHz, therefore the calibrator divider ratio (CALDIV, ST6 Register) must be set

accordingly.

When the PLL is configured in Integer mode only (NINT ≥ 512, see Section 7.3: PLL N

divider ) the calibrator divider should be by-passed (CALDIV = 1). In such a case, if the

setup of the application requires a PFD frequency higher than 250 kHz the calibration

procedure must be executed in two steps as follows:

VCO calibration. Configure all the device registers (see Section 7.18: Example

settings of the values N (ST0 Register) and R (ST3 Register) so that FPFD is ≤ 250 kHz.

Final operating setup. Adjust the values N and R properly in order to program the

device with the desired setup configuration (VCO and PFD frequency) setting also the

VCO_CALB_DISABLE bit set to ‘1’ (ST0 Register).

The above limitation of CALBCLK ≤ 250 kHz is valid for those applications which require the

PLL to stay in lock to the same frequency for a long time (experiencing a significant

temperature drift) without any user action. In such a case the calibration procedure must

select the optimal pair VCO/WORD able to guarantee the PLL lock condition over a

temperature drift defined by the

ΔTLOCK parameter (see Section 8.3: Robust VCO

calibration over full temperature range).

If the application requires a continuous hopping among different frequencies the maximum

allowed CALBCLK is increased up to 1 MHz (valid for both fractional and Integer-only

modes). In this case the VCO calibration procedure, required for each VCO frequency

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