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STUW81300 датащи(PDF) 28 Page - STMicroelectronics

номер детали STUW81300
подробное описание детали  Wideband RF/microwave PLL fractional/integer frequency synthesizer with integrated VCOs and LDOs
PDF  63 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STUW81300 датащи(HTML) 28 Page - STMicroelectronics

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Circuit description
STuW81300
28/63
DS11314 Rev 7
7.7
Charge pump
This block consists of two matched current sources, Iup and Idown, which are controlled
respectively by the UP and DOWN PFD outputs. The nominal value of the output current
(ICP) is controlled by selecting one of 32 values by a 5-bit word.
The minimum value of the output current (ICP) is 158 µA.
The charge pump also includes compensation circuitry to take into account variation of
KVCO with VCO control voltage, which changes with temperature and process for a
specified frequency. The KVCO compensation block adjusts the nominal ICP value,
minimizing the variation of the product ICP x KVCO to keep the PLL bandwidth constant for
the specified frequency. In order to compensate the change of KVCO with frequency, the
user should manually adjust the ICP value to keep the PLL bandwidth constant.
In addition, the charge-pump output stage can operate with a 3.3 V to 4.5 V supply voltage.
The LDO_4V5, programmable at 3.3 V and 4.5 V can be used for this purpose.
7.8
Fast lock mode
The fast-lock feature can be enabled to trade fast settling time against spurs rejection,
performance parameters which generally require different settings of PLL bandwidth
(narrow for better spurs rejection and wide for fast settling time).
A narrow bandwidth for low spurs can be designed for the lock state while a wide bandwidth
can be designed for the PLL transients.
The wide bandwidth is achieved during the transient by increasing the charge pump current
and reducing accordingly the dumping resistor value of the loop filter in order to keep the
phase margin of the PLL constant. The duration of the PLL wide band mode, in terms of
number of PFD cycles, is set by programming the fast-lock 13 bit counter.
Table 8. Current value versus selection
CPSEL4
CPSEL3
CPSEL2
CPSEL1
CPSEL0
Current
Value
000
00
-
0
000
01
IMIN
158 µA
000
10
3*IMIN
316 µA
...
...
...
...
...
...
...
111
01
29*IMIN
4.58 mA
111
10
30*IMIN
4.74 mA
111
11
31*IMIN
4.9 mA



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