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STUW81300 датащи(PDF) 36 Page - STMicroelectronics |
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STUW81300 датащи(HTML) 36 Page - STMicroelectronics |
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36 / 63 page ![]() Circuit description STuW81300 36/63 DS11314 Rev 7 7.16 STuW81300 register descriptions ST0 Register Address: STuW81300BaseAddress + 0x00 Type: R/W Description: Master register. N divider, CP current 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 765 4321 0 WRW RW RW RW RW [26] VCO_CALB_DISABLE: Must be set to ‘0’ 1: disable the VCO calibrator (Note: this bit is of type write-only and cannot be read. A read operation always returns 1) [25:21] CP_SEL: set charge pump pulse current value (0 to 4.9 mA; step ~158 μA) 00000: (0) set ICP=0 00001: (1) set ICP=158 μA 00010: (2) set ICP=316 μA 11110: (30) set ICP=4.74 mA 11111: (31) set ICP=4.90 mA [20:19] PFD_DEL: set PFD anti-backlash delay / down-split current value 00: (0) 1.2 ns / 0 A (default) 01: (1) 1.9 ns / 0.25*ICP 10: (2) 2.5 ns / 0.5*ICP 11: (3) 3.0 ns / 0.75*ICP [18] RESERVED: must be set to ‘0’ [17] RESERVED: must be set to ‘0’ [16:0] N: Set integer part of N divider ratio (NINT) For NINT ≥ 512, fractional mode is not allowed (FRAC and MOD settings are ignored) |
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