8.5

Switching modes

The following sections describe the switching modes which are used by the device depending on the output

power to be delivered.

8.5.1

Normal switching mode

The controller operates a non-complementary active clamp converter. The main waveforms are shown in

Figure 8.

Figure 8. Normal operation waveforms

Ipri

Isec

Vlsd

Vlsg

Vhsg

Vsrg

1

2 3

4

5

7

6

The converter operation is similar to a traditional QR flyback, with the addition of a clamp switch to recover the

energy in the transformer leakage inductance at low-side turn-off and uses the energy to obtain soft switching

at low-side turn-on. In particular, the high-side is turned on for a time proportional to the input/output conversion

ratio in order to limit the circulating current to what is required to obtain soft switching at low-side turn-on. The

synchronous rectifier is kept on after high-side turn-on to obtain zero secondary side current before the high-side

is turned off and a new cycle is started through a resonance between the leakage inductance and the clamp

capacitor.

The phases are as follows:

1.

LS turn-on. The on timing and peak current are defined by the secondary side controller. The phase

terminates when the primary side peak current comparator is triggered.

2.

Deadtime. A deadtime is inserted between LS turn-on and HS / SR turn-on.

3.

SR turn-on / first HS turn-on. When the secondary side ZCD12 comparator is triggered, the secondary

side commands the turn-on of both SR and HS switches. During this phase the current in the primary side

leakage inductance drops to 0, while the energy is stored in the clamp capacitor. The HS switch turn-on is

not strictly required but improves the efficiency of the system by avoiding conduction through the HS body

diode. The duration of the first HS pulse can be controlled by the configuration parameters.

4.

During phase 4 current flows on the secondary side through the SR FET. The phase terminates when the

IZCD comparator is triggered (current on the secondary side reached 0).

5.

HS is turned on to recover the energy stored in the clamp capacitor in phase 3 and to store energy in the

primary side inductance to force a soft switching. During this phase the leakage inductance resonates with

the clamp capacitor, creating a bump on the output current. When the current reaches 0 the SR is turned

off. The duration of this phase is configured through programmable parameters.

6.

Extra HS turn-on time may be added to increase the energy stored in the magnetizing inductor, in

particular at low output and high input voltage. The firmware calculates the duration of this phase based on

parameters.

7.

Deadtime. The deadtime between HS and LS is controlled by the secondary side through the parameter

DT_HVG_LVG.

ST-ONEMP

Switching modes

DS13989 - Rev 2

page 19/39