8

Device operation

8.1

Typical application schematic

The following image is a simplified schematic for the typical application.

Figure 4. Typical configuration

CC1/2

GPIO0 (PSHARE)

PGND

LEB

P3V3

CCLAMP

CBULK

RSNS_PRI

COUT

COUT

RSNS_IOUT

HS

OR

SR

LS

AC

AC

VOUT

VOUT

VDRV

VDRV

RZCD_PU

RZCD

n:1

Second Port

Controller &

DC/DC

GPIO1 (PGOOD)

The ST-ONEMP is a very intergrated IC, which needs a few external components to build a complete system. On

the primary side:

•

An AC full wave power rectifier connected to a bulk capacitor.

•

Two rectifier diodes to provide HV voltage to ST-ONEMP IC both for high voltage startup and AC brownout

and disconnection detection.

•

An integrated half bridge power stage (e.g ST MasterGaN) or Gate driver + FETs connected to the

transformer primary winding.

•

A clamp capacitor to store the residual energy in the transformer leakage inductance.

•

An auxiliary winding power supply for the IC PVCC, also used to perform overvoltage function during the

soft-start.

On the secondary side:

•

A synchronous rectifier FET is connected to the SRGD pin.

•

A cascode FET connected to the SRVDS pin to provide synchronous rectifier drain voltage sense while

limiting the voltage on the pin below its AMR.

•

An N-channel MOSFET connected to ORGD pin used as load switch to disconnect the output voltage as

required by USB-PD power supplies.

•

A sense resistor is connected to CSM/CSP pins to read the output current.

•

A capacitor and two diodes connected to the PUMP pin to implement a charge pump providing the driving

voltage to the synchronous rectifier.

ST-ONEMP

Device operation

DS13989 - Rev 2

page 15/39