IZCD: This comparator compares SRVDS with SSGND. It is used to detect the zero crossing of the current during

SR mos conduction phase. Referring to Figure 5, the comparator is triggered in instant 2.

SR1V: This comparator compares SRVDS with a 1 V threshold. It is used to detect when the primary side low

side FET is turned off, making the voltage across the SR MOS drop. This comparator commands the turn-on of

the SR mos. Referring to Figure 5, the comparator is triggered in instant 1.

8.2.5

Secondary side current sense resistor

The secondary side current sense has a full-scale range VCSFSR equal to 25 mV. The current sense is chosen

according to the formula:

RsenseSec<VCSFSR

IMAX

(5)

8.3

High voltage startup

The ST-ONEMP is equipped with internal HV start-up circuitry dedicated to supplying the IC during the initial

start-up phase, before the self-supply winding is operating. An external capacitor connected to the PVCC pin is

charged by the HV start-up circuitry, connected to the HV pin.

When the power is applied to the circuit and the voltage on the input is high enough, the HV generator is

sufficiently biased to start operating, thus it draws the current IHVON through the HV pin and charges the capacitor

connected between PVCC pin and ground. This charging current is limited at 1 mA in case the voltage on PVCC

is lower than VPVCC_SO, in order to prevent excessive IC dissipation if the pin is accidentally shorted to ground.

As the PVCC voltage reaches the start-up threshold (VPVCCOn) the chip starts operating, and the control logic

disables the HV generator.

The IC is powered by the energy stored in the PVCC capacitor until the auxiliary winding develops a voltage high

enough to sustain the operation.

8.4

Soft-start

As soon as the proper conditions for startup are met, the primary side controller performs a soft-start

autonomously until the secondary side is powered and able to take control of the switching.

During soft-start the IC operates in constant off-time, peak current mode. The user can set the off-time by

connecting a resistor from the OSC pin to ground.

The peak current during soft-start is determined by comparing the SS pin and ISEN pin voltages. Connecting a

capacitor to the SS sets the soft-start duration.

The primary side controlled soft-start ends as the secondary side takes control of the conversion.

During the soft-start the high-side is controlled in complementary mode, with deadtimes determined by a resistor

connected between DT and ground. Note that during soft-start both the deadtimes are equal to TDT_SS which is

approximately double the value used in normal mode for LS to HS.

As the voltage on the secondary side reaches VSVCCON, the secondary side IC boots up, takes control of the

conversion and the converter starts to operate in normal mode as described in Section 8.5.1 . The secondary

side controller continues the soft-start operating in closed loop and ramping the SVCC voltage to 5 V, then the

soft-start ends.

Figure 6. Soft-start waveforms: primary side

controlled soft-start phase

Figure 7. Soft-start waveforms: switch to

secondary side control

ST-ONEMP

High voltage startup

DS13989 - Rev 2

page 18/39