M58LR128FT datasheet(16/82 Pages) STMICROELECTRONICS

16 / 82 page

M58LR128FT, M58LR128FB

16/82

–

Read CFI Query.

Additionally, if the suspended operation was erase

then the following commands are also accepted:

–

Clear Status Register

–

Program (except in erase-suspended

block)

–

Block Lock

–

Block Lock-Down

–

Block Unlock.

During an erase suspend the block being erased

can be protected by issuing the Block Lock or

Block Lock-Down commands. When the Program/

Erase Resume command is issued the operation

will complete.

It is possible to accumulate multiple suspend oper-

ations. For example: suspend an erase operation,

start a program operation, suspend the program

operation, then read the array.

If a Program command is issued during a Block

Erase Suspend, the erase operation cannot be re-

sumed until the program operation has completed.

The Program/Erase Suspend command does not

change the read mode of the banks. If the sus-

pended bank was in Read Status Register, Read

Electronic signature or Read CFI Query mode the

bank remains in that mode and outputs the corre-

sponding data.

Refer to Dual Operations section for detailed infor-

mation about simultaneous operations allowed

during Program/Erase Suspend.

During a Program/Erase Suspend, the device can

be placed in standby mode by taking Chip Enable

to VIH. Program/erase is aborted if Reset, RP,

goes to VIL.

See APPENDIX C., Figure 24., Program Suspend

& Resume Flowchart and Pseudo Code, and Fig-

ure 26., Erase Suspend & Resume Flowchart and

Pseudo Code, for flowcharts for using the Pro-

gram/Erase Suspend command.

Program/Erase Resume Command

The Program/Erase Resume command is used to

restart the program or erase operation suspended

by the Program/Erase Suspend command. One

Bus Write cycle is required to issue the command.

The command can be issued to any address.

The Program/Erase Resume command does not

change the read mode of the banks. If the sus-

pended bank was in Read Status Register, Read

Electronic signature or Read CFI Query mode the

bank remains in that mode and outputs the corre-

sponding data.

If a Program command is issued during a Block

Erase Suspend, then the erase cannot be re-

sumed until the program operation has completed.

See APPENDIX C., Figure 24., Program Suspend

& Resume Flowchart and Pseudo Code, and Fig-

ure 26., Erase Suspend & Resume Flowchart and

Pseudo Code, for flowcharts for using the Pro-

gram/Erase Resume command.

Protection Register Program Command

The Protection Register Program command is

used to program the user One-Time-Programma-

ble (OTP) segments of the Protection Register and

the two Protection Register Locks.

The device features 16 OTP segments of 128 bits

and one OTP segment of 64 bits, as shown in Fig-

ure 5., Protection Register Memory Map.

The segments are programmed one Word at a

time. When shipped all bits in the segment are set

to ‘1’. The user can only program the bits to ‘0’.

Two Bus Write cycles are required to issue the

Protection Register Program command.

■

The first bus cycle sets up the Protection

■

The second latches the address and data to

be programmed to the Protection Register and

starts the Program/Erase Controller.

Read operations to the bank being programmed

output the Status Register content after the pro-

gram operation has started.

Attempting to program a previously protected Pro-

tection Register will result in a Status Register er-

ror.

The Protection Register Program cannot be sus-

pended.

The two Protection Register Locks are used to

protect the OTP segments from further modifica-

tion. The protection of the OTP segments is not re-

versible. Refer to Figure 5., Protection Register

Memory Map, and Table 8., Protection Register

Locks, for details on the Lock bits.

See APPENDIX C., Figure 28., Protection Regis-

ter Program Flowchart and Pseudo Code, for a

flowchart for using the Protection Register Pro-

gram command.

Set Configuration Register Command

The Set Configuration Register command is used

to write a new value to the Configuration Register.

Two Bus Write cycles are required to issue the Set

Configuration Register command.

■

The first cycle sets up the Set Configuration

corresponding to the Configuration Register

content.

■

The second cycle writes the Configuration

The Configuration Register data must be written

as an address during the bus write cycles, that is

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