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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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68HC705SP7 датащи(PDF) 67 Page - NXP Semiconductors |
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68HC705SP7 датащи(HTML) 67 Page - NXP Semiconductors |
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67 / 230 page  Resets Reset States MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0 General Release Specification Resets 5.6.7 Analog Subsystem A reset has the following effects on the analog subsystem: • Clears all the bits in the multiplex register (AMUX) bits except the hold switch bit (HOLD) which is set • Clears all the bits in the analog control register (ACR) • Clears all the bits in the analog status register (ASR) A reset, therefore, connects the negative input of comparator 2 to the channel selection bus, which is switched to VSS. Both comparators are set up as non-inverting (a higher positive voltage on the positive input results in a positive output) and both are powered down. The current source and discharge device on the PB0/AN0 pin is disabled and powered down. Any analog subsystem interrupt flags are cleared and the analog interrupt is disabled. Direct drive by comparator 1 to the PB4 pin and the voltage offset to the sample capacitor are disabled (if both are enabled by the OPT bit being set in the MOR). 5.6.8 External Oscillator and Internal Low-Power Oscillator A reset presets the oscillator select bits (OM1 and OM2) in the interrupt status and control register (ISCR) such that the device runs from the internal oscillator (OM1 = 0, OM2 = 1) which has the following effects on the oscillators: • The internal low-power oscillator is enabled and selected • The external oscillator is disabled • The CPU bus clock is driven from the internal low-power oscillator Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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