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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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68HC705SP7 датащи(PDF) 55 Page - NXP Semiconductors |
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68HC705SP7 датащи(HTML) 55 Page - NXP Semiconductors |
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55 / 230 page  Interrupts Core Timer Interrupts MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0 General Release Specification Interrupts IRQR — Interrupt Request Reset This write-only bit clears the IRQF flag bit and prevents redundant execution of interrupt routines. Writing a logic one to IRQR clears the IRQF. Writing a logic zero to IRQR has no effect. IRQR always reads as a logic zero. Reset has no affect on IRQR. 1 = Clear IRQF flag bit 0 = No effect 4.7 Core Timer Interrupts The core timer can generate the following interrupts: • Timer overflow interrupt • Real-time interrupt Setting the I bit in the condition code register disables core timer interrupts. The controls and flags for these interrupts are in the core timer status and control register (CTSCR) located at $0008. 4.7.1 Core Timer Overflow Interrupt An overflow interrupt request occurs if the core timer overflow flag (TOF) becomes set while the core timer overflow interrupt enable bit (TOFE) is also set. The TOF flag bit can be reset by writing a logical one to the CTOFR bit in the CTSCR or by a reset of the device. 4.7.2 Real-Time Interrupt A real-time interrupt request occurs if the real-time interrupt flag (RTIF) in the CTSCR becomes set while the real-time interrupt enable bit (RTIE) is also set. The RTIF flag bit can be reset by writing a logical one to the RTIFR bit in the CTSCR or by a reset of the device. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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