68HC705SP7 datasheet(57/230 Pages) NXP

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Interrupts

Serial Interrupts

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Interrupts

4.8.3 Timer Overflow Interrupt

A timer overflow interrupt occurs if the timer overflow flag (TOF)

becomes set while the timer overflow interrupt enable bit (TOIE) is also

set. The TOF flag bit is in the TSR and the TOIE enable bit is in the TCR.

The TOF flag bit is cleared by a read of the TSR with the TOF flag bit set,

and then followed by an access to the LSB of the timer registers (TMRL)

or by reset. The TOIE enable bit is unaffected by reset.

4.9 Serial Interrupts

The simple serial interface can generate the following interrupts:

•

Receive sequence complete

•

Transmit sequence complete

Setting the I bit in the condition code register disables serial interrupts.

The controls for these interrupts are in the serial control register (SCR)

located at $000A and in the status bits in the serial status register (SSR)

located at $000B.

A transfer complete interrupt occurs if the serial interrupt flag (SPIF)

becomes set while the serial interrupt enable bit (SPIE) is also set. The

SPIF flag bit is in the serial status register (SSR) located at $000B, and

the SPIE enable bit is located in the serial control register (SCR) located

at $000A. The SPIF flag bit is cleared by a read of the SSR with the SPIF

flag bit set, and then followed by a read or write to the serial data register

(SDR) located at $000C. The SPIF flag bit can also be reset by writing a

one to the SPIR bit in the SCR.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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