Data Sheet

LT3073

analog.com

Rev 0.

25 of 37

REF – Voltage Reference

The REF pin is the voltage output of the internal current reference feeding into a resistor DAC. A 4.7µF REF capacitor

to GND decreases reference voltage noise, and soft starts OUT at enable. Soft-start time is determined by the value

of the REF capacitor used.

The REF pin must not be DC loaded by anything except for applications that parallel other LT3073 regulators for

higher output currents. See the Paralleling Devices for Higher Output Current section for further details.

Output Voltage Digital Margining

A digital input pin, MARG, is employed by offsetting the internal reference and, likewise the output. Grounding the

MARG pin offsets the output by –2.5%. Similarly, pulling the MARG pin up to the BIAS pin offsets the output by +2.5%.

Enable Function – Turning ON and OFF

The EN pin enables/disables the OUT and REF pins. Pulling EN pin low places the regulator into “nap” mode. In nap

mode, the quiescent current decreases to less than 10µA.

Drive the EN pin with either a digital logic port, or an open-collector NPN or an open-drain NMOS terminated with a

pull-up resistor to VBIAS. The pull-up resistor must be less than 200kΩ to meet the VIH condition of the EN pin. If unused,

connect the EN pin to BIAS.

BIAS Under Voltage Lock Out

An internal under voltage lock out (UVLO) comparator monitors the BIAS rail. If VBIAS drops below the UVLO threshold,

all functions shut down, the pass transistors are gated off, and output currents fall to zero. The typical BIAS pin UVLO

threshold is 2.2V on the rising edge of VBIAS. The UVLO circuit incorporates about 130mV of hysteresis on the falling

edge of VBIAS.

High Efficiency Linear Regulator – Input-to-Output Voltage Control

The VIOC pin controls an upstream switching converter to maintain a constant voltage across the LT3073, regardless

of the LDO’s output voltage. This maximizes efficiency while maintaining PSRR performance. The VIOC pin is the

output of a fast amplifier and equals to (VIN – VOUT) + 800mV. As shown in Figure 70, the VIOC feature is simple to use.

In the case of VFB ≥ 1V, connect the VIOC pin to the upstream switching converter’s feedback (FB) pin. This will regulate

the LT3073’s input-to-output differential to the switching converter’s feedback voltage minus 800mV. When

paralleling multiple LT3073s, connect the VIOC pin of one of the LT3073 to the upstream switching converter’s

feedback pin and float the remaining VIOC pin(s). When LT3073 is turned off, VINLDO is clamped to a voltage set by

VFBSWITCHER x (R1 + R2)/R1

Figure 70.VIOC Basic Operation

51kΩ

806Ω

R1

2.2µF

22µF

4.7µF

800mV

VIN

OUT

BIASF

LT3073

VOUTLDO = 0.5V

IOUT(MAX) = 3A

VO2

VO1

VO0

VBIAS

3.3V

IN

EN

VIOC

MARG

GND

SENSE

TEMP

IMON

POWER

GOOD

BIAS

PG

REF

UPSTREAM

DC TO DC

CONVERTER

VFB >= 1V

VIN

EN/UV

GND

SW

FB

R2

VINLDO

1×

+ –

VFBSWITCHER