Data Sheet

LT3073

analog.com

Rev 0.

27 of 37

Stability and Output Capacitance

The LT3073 feedback loop requires a minimum output capacitance of 10μF for stability. ADI recommends mounting

low ESR, X5R or X7R ceramic capacitors near the LT3073 OUT and GND pins. Include wide routing planes for OUT and

GND to minimize inductance. If possible, mount the regulator immediately adjacent to the application load to

minimize distributed inductance for optimal load transient performance. Point-of-load applications present the

best-case layout scenario for extracting full LT3073 performance.

Additional ceramic capacitors distributed beyond the immediate decoupling capacitors are acceptable and

recommended at the point of the load because the distributed PCB inductance isolates them from the primary

compensation capacitors.

Many of the applications in which the LT3073 excels, such as FPGA, ASIC processor, or DSP supplies, typically require

a high-frequency decoupling capacitor network for the device being powered. This network generally consists of

many low-value ceramic capacitors in parallel. In parallel, multiple low-value capacitors present a favorable

frequency characteristic that reduces the parasitic inductance of the capacitors.

Consider the use of ceramic capacitors. Ceramic capacitors are manufactured with various dielectrics, each with

different temperatures and applied voltage behavior. The most common dielectrics are specified with EIA

temperature characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are suitable for providing

high capacitances in a small package, but they tend to have strong voltage and temperature coefficients, as shown

in Figure 72 and Figure 73. When used with a 5V regulator, a 16V 10μF Y5V capacitor can exhibit an effective value as

low as 1μF to 2μF for the DC bias voltage applied and over the operating temperature range. The X5R and X7R

dielectrics result in more stable characteristics and are more suitable for use as the output capacitor.

The X7R type has better stability across temperatures, while the X5R is less expensive and is available in higher

values. Care still must be exercised when using X5R and X7R capacitors; the X5R and X7R codes only specify the

operating temperature range and maximum capacitance change over temperature. Capacitance change due to DC

bias with X5R and X7R capacitors is better than Y5V and Z5U capacitors but can still be significant enough to drop

capacitor values below appropriate levels. Capacitor DC bias characteristics tend to improve as component case size

increases but expected capacitance at operating voltage should be verified. Voltage and temperature coefficients

are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device

generates a voltage across its terminals due to mechanical stress, similar to how a piezoelectric microphone works.

For a ceramic capacitor, the stress can be induced by vibrations in the system or thermal transients.

Figure 72. Ceramic Capacitor DC Bias Characteristics

Figure 73. Ceramic Capacitor Temperature Characteristics

20

0

–20

DC BIAS VOLTAGE (V)

0

2

4

6

8

10

12

Y5V

X5R

14

16

–40

–60

–80

–100

BOTH CAPACITORS ARE 16V

1210 CASE SIZE, 10µF

40

20

0

–20

DC BIAS VOLTAGE (V)

–50

–25

0

25

50

75

100

Y5V

X5R

125

–40

–60

–80

–100

BOTH CAPACITORS ARE 16V

1210 CASE SIZE, 10µF