LT3073AVPBF datasheet(10/37 Pages) AD

10 / 37 page

Data Sheet

LT3073

analog.com

Rev 0.

10 of 37

Table 5. Pin Descriptions

NAME

DESCRIPTION

Device Enable. EN pin enables/disables the output. Pulling this pin low pulls down the

reference, disables the output transistor, and disables auxiliary functions. Drive the EN

pin with either a digital logic port, or an open-collector NPN or an open-drain NMOS

terminated with a pull-up resistor to VBIAS. The pull-up resistor must be less than 200kΩ

to meet the VIH condition of the EN pin. If unused, connect the EN pin to BIAS.

2, 3, 4

VO0, VO1, VO2

Output Voltage Select. These tri-level pins combine to select a nominal output voltage

from 0.5V to 4.2V. The input logic low threshold is less than 300mV referenced to GND,

and the logic high threshold is greater than 1.97V referenced to GND. The range

between 0.95V and 1.15V defines the logic Hi-Z state. See Table 6 in the Applications

Information section that defines the VOUT versus VO0, VO1, and VO2 settings.

Power Good. The PG pin is an open-drain NMOS output that actively pulls low if EN is

low or if any one of these fault modes is detected:



VOUT is less than 93% of VOUT(NOMINAL) on the rising edge of VOUT.



VOUT is less than 90% of VOUT(NOMINAL) on the falling edge of VOUT.



VBIAS is less than its undervoltage lockout threshold.



The OUT-over-IN voltage detector activates.

VIOC

Voltage for In-to-Out Control. The LT3073 incorporates a unique tracking feature

(VIOC) to control the upstream switching regulator to maintain a constant voltage

across the LT3073 and minimize power dissipation. See the Applications Information

section for more information on proper control of the upstream switching regulator.

7, 8, 9,

Exposed

Pad 24

OUT

Output. Pins 7-9 and exposed pad 24 of the LQFN package are the electrical

connection to OUT. These pins supply power to the load. Connect all OUT pins for

proper performance and solder Pin 24 to the PCB for better thermal performance. A

minimum output capacitance of 10µF is required for stability. ADI recommends low

ESR, X5R or X7R dielectric ceramic capacitors for best performance. Large load

transient applications require larger output capacitors to limit peak voltage transients.

SENSE

Kelvin Sense for OUT. The SENSE pin is the inverting input to the error amplifier.

Optimum regulation is obtained when the SENSE pin is connected to the OUT pins of

the regulator. However, in critical applications, the resistance of PCB traces between

the regulator and the load causes small voltage drops, creating a load regulation error

at the point of load. Connecting the SENSE pin to the load instead of directly to OUT

eliminates this voltage error.

11, 12, 19 GND

Ground. To ensure proper electrical and thermal performance, connect all GND pins of

the package to the PCB ground.

REF

Reference Filter. This pin must not be externally loaded. Bypassing the REF pin to GND

with a 4.7µF capacitor decreases output voltage noise and provides a soft-start

function to the reference. ADI recommends the use of a high-quality, low-leakage

capacitor.

MARG

Output Voltage Digital Margining. Connecting this pin to GND adjusts the output

voltage by -2.5%. Connecting this pin to VBIAS adjusts the output voltage by +2.5%.

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