UPSD3422_V01 datasheet(35/300 Pages) STMICROELECTRONICS

35 / 300 page

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UPSD3422, UPSD3433, UPSD3434, UPSD3454

8032 MCU core performance enhancements

35/300

four MCU clocks). But it is also important to understand PFQ operation on multi-cycle

instructions.

5.2

PFQ example, multi-cycle instructions

Let us look at a string of two-byte, two-cycle instructions in Figure 8 on page 35. There are

three instructions executed sequentially in this example, instructions A, B, and C. Each of

the time divisions in the figure is one machine-cycle of four clocks, and there are six phases

to reference in this discussion. Each instruction is pre-fetched into the PFQ in advance of

execution by the MCU. Prior to Phase 1, the PFQ has pre-fetched the two instruction bytes

(A1 and A2) of Instruction A. During Phase one, both bytes are loaded into the MCU

execution unit. Also in Phase 1, the PFQ is pre-fetching Instruction B (bytes B1 and B2) from

program memory. In Phase 2, the MCU is processing Instruction A internally while the PFQ

is pre-fetching Instruction C. In Phase 3, both bytes of instruction B are loaded into the MCU

execution unit and the PFQ begins to pre-fetch bytes for the next instruction. In Phase 4

Instruction B is processed.

The UPSD34xx MCU instructions are an exact 1/3 scale of all standard 8032 instructions

with regard to number of cycles per instruction. Figure 9 on page 36 shows the equivalent

instruction sequence from the example above on a standard 8032 for comparison.

5.3

Aggregate performance

The stream of two-byte, two-cycle instructions in Figure 8 on page 35, running on a 40 MHz,

5 V, UPSD34xx will yield 5 MIPs. And we saw the stream of one- or two-byte, one-cycle

instructions in Figure 6 on page 33, on the same MCU yield 10 MIPs. Effective performance

will depend on a number of things: the MCU clock frequency; the mixture of instructions

types (bytes and cycles) in the application; the amount of time an empty PFQ stalls the MCU

(mix of instruction types and misses on Branch Cache); and the operating voltage. A 5 V

UPSD34xx device operates with four memory wait states, but a 3.3 V device operates with

five memory wait states yielding 8 MIPS peak compared to 10 MIPs peak for 5 V device.

The same number of wait states will apply to both program fetches and to data

READ/WRITEs unless otherwise specified in the SFR named BUSCON.

In general, a 3X aggregate performance increase is expected over any standard 8032

application running at the same clock frequency.

Figure 8.

PFQ operation on multi-cycle instructions

Three 2-byte, 2-cycle Instructions on uPSD34xx

PFQ

MCU

Execution

Inst A, Byte 1&2 Inst B, Byte 1&2 Inst C, Byte 1&2

Next Inst

Previous Instruction

Process A

Process B

AI10432

Process C

Continue to Pre-Fetch

Next Inst

4-clock

Macine Cycle

Instruction A

Instruction B

Instruction C

Pre-Fetch

Inst A

Pre-Fetch Inst B and C

Pre-Fetch next Inst

Phase 1

Phase 2

Phase 3

Phase 4

Phase 6

Phase 5

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