UPSD3422_V01 datasheet(88/300 Pages) STMICROELECTRONICS

88 / 300 page

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MCU bus interface

UPSD3422, UPSD3433, UPSD3434, UPSD3454

88/300

It is not possible to specify in the BUSCON register a different number of MCU_CLK periods

for various address ranges. For example, the user cannot specify 4 MCU_CLK periods for

RD read cycles to one address range on the PSD module, and 5 MCU_CLK periods for RD

read cycles to a different address range on an external device. However, the user can

specify one number of clock periods for PSEN read cycles and a different number of clock

periods for RD or WR cycles (see Figure 21 on page 88).

18.5

Controlling the PFQ and BC

The BUSCON register allows firmware to enable and disable the PFQ and BC at run-time.

Sometimes it may be desired to disable the PFQ and BC to ensure deterministic execution.

The dynamic action of the PFQ and BC may cause varying program execution times

depending on the events that happen prior to a particular section of code of interest. For this

reason, it is not recommended to implement timing loops in firmware, but instead use one of

the many hardware timers in the UPSD34xx. By default, the PFQ and BC are enabled after

a reset condition.

Important note: Disabling the PFQ or BC will seriously reduce MCU performance.

Figure 21.

A RD or PSEN bus cycle set to 5 MCU_CLK

The PSEN cycle is 16-bit, while the RD cycle is 8-bit only.

A PSEN bus cycle in progress may be aborted before completion if the PFQ and Branch Cache (BC)

determines the current code fetch cycle is not needed.

Whenever the same number of MCU_CLK periods is specified in BUSCON for both PSEN and RD cycles,

the bus cycle timing is typically identical for each of these types of bus cycles. In this case, the only time

PSEN read cycles are longer than RD read cycles is when the PFQ issues a stall while reloading. PFQ

stalls do not affect RD read cycles. By comparison, in many traditional 8051 architectures, RD bus cycles

are always longer than PSEN bus cycles.

Table 49.

BUSCON: bus control register (SFR 9Dh, reset value EBh)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EPFQ

EBC

WRW[1:0]

RDW[1:0]

CW[1:0]

A0-A15

MCU Clock

ALE

AD0-AD15

D0-D15

(1)

5-Clock Bus Cycle

RD/PSEN

(2,3)

AI10436

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