UPSD3422_V01 datasheet(20/300 Pages) STMICROELECTRONICS

20 / 300 page

Obsolete

Product(s)

- Obsolete

Product(s)

Obsolete

Product(s)

- Obsolete

Product(s)

Description

UPSD3422, UPSD3433, UPSD3434, UPSD3454

20/300

Description

The Turbo Plus UPSD34xx Series combines a powerful 8051-based microcontroller with a

flexible memory structure, programmable logic, and a rich peripheral mix to form an ideal

embedded controller. At its core is a fast 4-cycle 8032 MCU with a 4-byte instruction

prefetch queue (PFQ) and a 4-entry fully associative branching cache (BC). The MCU is

connected to a 16-bit internal instruction path to maximize performance, enabling loops of

code in smaller localities to execute extremely fast. The 16-bit wide instruction path in the

Turbo Plus Series allows double-byte instructions to be fetched from memory in a single

memory cycle. This keeps the average performance near its peak performance (peak

performance for 5 V, 40 MHz Turbo Plus UPSD34xx is 10 MIPS for single-byte instructions,

and average performance will be approximately 9 MIPS for mix of single- and multi-byte

instructions).

USB 2.0 (full speed, 12Mbps) is included, providing 10 endpoints, each with its own 64-byte

FIFO to maintain high data throughput. Endpoint 0 (control endpoint) uses two of the 10

endpoints for In and Out directions, the remaining eight endpoints may be allocated in any

mix to either type of transfers: Bulk or Interrupt.

Code development is easily managed without a hardware in-circuit emulator by using the

serial JTAG debug interface. JTAG is also used for in-system programming (ISP) in as little

as 10 seconds, perfect for manufacturing and lab development. The 8032 core is coupled to

programmable system device (PSD) architecture to optimize the 8032 memory structure,

offering two independent banks of Flash memory that can be placed at virtually any address

within 8032 program or data address space, and easily paged beyond 64 Kbytes using on-

chip programmable decode logic.

Dual Flash memory banks provide a robust solution for remote product updates in the field

through in-application programming (IAP). Dual Flash banks also support EEPROM

emulation, eliminating the need for external EEPROM chips.

General-purpose programmable logic (PLD) is included to build an endless variety of glue-

logic, saving external logic devices. The PLD is configured using the software development

tool, PSDsoft Express, available from the web at www.st.com/psm, at no charge.

The UPSD34xx also includes supervisor functions such as a programmable watchdog timer

and low-voltage reset.

Note:

For a list of known limitations of the UPSD34xx devices, please refer to Section 34:

Important notes.

Obsolete

Product(s)

- Obsolete

Product(s)

UPSD3422 датащи(PDF) 20 Page - STMicroelectronics

UPSD3422 датащи(HTML) 20 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL