MCT8317A datasheet(14/161 Pages) TI1

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at TJ = –25°C to +125°C, VVM = 6 to 18 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 12 V

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

tLOW

Low period of the SCL clock

1.3

µs

tHIGH

High period of the SCL clock

0.6

µs

tSU_STA

Set-up time for a repeated START

condition

SCL rise (Tr 30% to 70% = 180ns-300ns),

SDA fall (Tf 70% to 30% = 6.5ns-106.5ns)

0.6

µs

tHD_DAT

I2C Start Data Hold Time (1)

SCL fall (Tf 70% to 30% =

6.5ns-106.5ns),

SDA rise (Tr 30% to 70% = 180ns-300ns)

or fall (Tf 70% to 30% = 6.5ns-106.5ns)

0 (2)

(3)

µs

I2C Input Data Transfer Hold Time (1)

SCL fall (Tf 70% to 30% =

6.5ns-106.5ns),

SDA rise (Tr 30% to 70% = 180ns-300ns)

or fall (Tf 70% to 30% =6.5ns-106.5ns)

0 (2)

(3)

µs

tSU_DAT

I2C False Start/Stop Data Set-up Time

SCL rise (Tr 30% to 70% = 180ns-300ns),

SDA rise (Tr 30% to 70% = 180ns-300ns)

or fall (Tf 70% to 30% = 6.5ns-106.5ns)

100 (4)

I2C Input Data Transfer Set-up Time

SCL rise (Tr 30% to 70% = 180ns-300ns),

SDA rise (Tr 30% to 70% = 180ns-300ns)

or fall (Tf 70% to 30% = 6.5ns-106.5ns)

100 (4)

Rise time for both SDA and SCL signals

300

Fall time of both SDA and SCL signals (2)

(5) (6) (7)

4.36

300

tSU_STO

Set-up time for STOP condition

SCL rise (Tr 30% to 70% = 180ns-300ns),

SDA rise (Tr 30% to 70% = 180ns-300ns)

0.6

µs

tBUF

Bus free time between STOP and START

condition

1.3

µs

Capacitive load for each bus line (8)

150

tVD_DAT

Data valid time (9)

0.9 (3)

µs

tVD_ACK

Data valid acknowledge time (10)

0.9 (3)

µs

VnL

Noise margin at the Low level

No chattering at output for noise at VOL

0.12

Vnh

Noise margin at the High level

No chattering at output for noise at VOH

0.24

(1)

tHD_DAT is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.

(2)

A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

(3)

The maximum tHD_DAT could be 3.45 us and .9 us for Standard-mode and Fast-mode, but must be less than the maximum of tVD_DAT or

tVD_ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If

the clock stretched the SCL, the data must be valid by the set-up time before it releases the clock.

(4)

A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU_DAT 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period if the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU_DAT = 1000 + 250 = 1250 ns (according to the

Standard-mode I2C-bus specification) before the SCL line is released. Also, the acknowledge timing must meet this set-up time.

(5)

If mixed with Hs-mode devices, faster fall times according to Table 10 are allowed.

(6)

The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified

at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines

without exceeding the maximum specified tf.

(7)

In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should

allow for this when considering bus timing.

(8)

The maximum bus capacitance allowable may vary from the value depending on the actual operating voltage and frequency of the

application.

(9)

tVD_DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

(10) tVD_ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

MCT8317A

SLLSFQ2 – JANUARY 2023

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