MCT8317A datasheet(13/161 Pages) TI1

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7.6 Characteristics of the SDA and SCL bus for Standard and Fast mode

at TJ = –25°C to +125°C, VVM = 6 to 18 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 12 V

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

Standard-mode

fSCL

SCL clock frequency

100

kHz

tHD_STA

Hold time (repeated) START condition

After this period, the first clock pulse is

generated

SCL fall (Tf 70% to 30% =

6.5ns-106.5ns),

SDA fall (Tf 70% to 30% = 6.5ns-106.5ns)

µs

tLOW

Low period of the SCL clock

4.7

µs

tHIGH

High period of the SCL clock

µs

tSU_STA

Set-up time for a repeated START

condition

SCL rise (Tr 30% to 70% =

600ns-1000ns),

SDA fall (Tf 70% to 30% = 6.5ns-106.5ns)

4.7

µs

tHD_DAT

I2C Start Data Hold Time (1)

SCL fall (Tf 70% to 30% =

6.5ns-106.5ns),

SDA rise (Tr 30% to 70%=

600ns-1000ns) or fall (Tf 70% to 30% =

6.5ns-106.5ns)

0 (2)

(3)

µs

I2C Input Data Transfer Hold Time (1)

SCL fall (Tf 70% to 30% =

6.5ns-106.5ns),

SDA rise (Tr 30% to 70%=

600ns-1000ns) or fall (Tf 70% to 30% =

6.5ns-106.5ns)

0 (2)

(3)

µs

tSU_DAT

I2C False Start/Stop Data Set-up Time

SCL rise (Tr 30% to 70% =

600ns-1000ns),

SDA rise (Tr 30% to 70%=

600ns-1000ns) or fall (Tf 70% to 30% =

6.5ns-106.5ns)

250

I2C Input Data Transfer Set-up Time

SCL rise (Tr 30% to 70% =

600ns-1000ns),

SDA rise (Tr 30% to 70%=

600ns-1000ns) or fall (Tf 70% to 30% =

6.5ns-106.5ns)

250

Rise time for both SDA and SCL signals

1000

Fall time of both SDA and SCL signals (2)

(5) (6) (7)

300

tSU_STO

Set-up time for STOP condition

SCL rise (Tr 30% to 70% =

600ns-1000ns),

SDA rise (Tr 30% to 70% =

600ns-1000ns)

µs

tBUF

Bus free time between STOP and START

condition

4.7

µs

Capacitive load for each bus line (8)

400

tVD_DAT

Data valid time (9)

3.45 (3)

µs

tVD_ACK

Data valid acknowledge time (10)

3.45 (3)

µs

VnL

Noise margin at the Low level

For each connected device (including

hysteresis)

0.12

Vnh

Noise margin at the High level

For each connected device (including

hysteresis)

0.24

Fast-mode

fSCL

SCL clock frequency

400

kHz

tHD_STA

Hold time (repeated) START condition

After this period, the first clock pulse is

generated

SCL fall (Tf 70% to 30% =

6.5ns-106.5ns),

SDA fall (Tf 70% to 30% = 6.5ns-106.5ns)

0.6

µs

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MCT8317A

SLLSFQ2 – JANUARY 2023

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