MCT8317A datasheet(53/161 Pages) TI1

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8.3.18.1 FG Output Frequency

The FG output frequency can be configured by FG_DIV_FACTOR. In MCT8317A, FG toggles once every

commutation cycle if FG_DIV_FACTOR is set to 0000b. Many applications require the FG output to provide a

pulse for every mechanical rotation of the motor. Different FG_DIV_FACTOR configurations can accomplish this

for 2-pole up to 30-pole motors.

Figure 8-42 shows the FG output when MCT8317A has been configured to provide FG pulses once every

commutation cycle (electrical cycle/3), once every electrical cycle (2 poles), once every two electrical cycle (4

poles), once every three electrical cycles (6 poles), once every four electrical cycles (8 poles), and so on.

Phase A

Voltage

FG_DIV_FACTOR = 0000b

(Commuta on cycle)

FG_DIV_FACTOR = 0001b

(Elec cycle)

FG_DIV_FACTOR = 0011b

(Elec cycle*3)

FG_DIV_FACTOR = 0100b

(Elec cycle*4)

FG_DIV_FACTOR = 0010b

(Elec cycle*2)

Figure 8-42. FG Frequency Divider

8.3.18.2 FG Open-Loop and Lock Behavior

During closed loop operation, the driving speed (FG output frequency) and the actual motor speed are

synchronized. During open-loop operation, however, FG may not reflect the actual motor speed. During motor-

lock condition, the FG output is driven high.

The MCT8317A provides three options for controlling the FG output during open loop, as shown in Figure 8-43.

The selection of these options is configured through FG_SEL.

If FG_SEL is set to,

• 00b: When in open loop, the FG output is based on the driving frequency.

• 01b: When in open loop, the FG output will be driven high.

• 10b: The FG output will reflect the driving frequency during open loop operation in the first motor start-up

cycle after power-on, sleep/standby; FG will be held high during open loop operation in subsequent start-up

cycles.

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MCT8317A

SLLSFQ2 – JANUARY 2023

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