MCP3465R datasheet(79/110 Pages) MICROCHIP

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DS20006414C-page 79

MCP3465R

6.9.3

INTERNAL CLOCK MODE WITH

EXTERNAL AMCLK CLOCK

OUTPUT (CLK_SEL[1:0] = 11)

This mode is accessed by writing CLK_SEL[1:0] = 11.

This mode defines the SCK pin as both the Serial Clock

input and the Analog Master Clock (AMCLK) output. In

regard to the MCLK clock domain, the SCK pin is an

output pin that shows a continuous clock, AMCLK, gen-

erated by the internal oscillator. In regard to the SCK

clock domain, the SCK pin is still the input pin for the dig-

ital interface. In this mode, the SCK and MCLK are equal

and the device becomes a fully synchronous system.

The MCU connected to the SPI port has to be config-

ured to receive the SCK output and to generate

synchronized commands with this output; it needs to be

in SPI client mode. When this mode is enabled and run-

ning, the transitions on the CS pin do not impact the

SCK output; AMCLK is always available on the SCK

output even if CS is logic high.

Considering that the SCK pin becomes an output in this

clock mode, the transitions to and from this mode need

special care in order to avoid bus contention errors on

the SCK pin. The transition to this mode from another

clock mode is detailed in Figure 6-15.

The transition is not immediate; it does not occur as

soon as the CLK_SEL[1:0] bits = 11 are written in the

CONFIG0 register. This writing resets the master clock

internally until a new command is launched (CS falling

edge). In this case, the SCK is configured as the

AMCLK output and always starts with a Logic Low state

when it is at the CS falling edge transition.

To avoid bus contention errors, it is recommended to

keep the SCK state to logic low, before having the first

CS falling edge, after the writing of the CLK_SEL[1:0]

bits in CONFIG0 (as shown in Figure 6-15).

Considering that the internal oscillator starts at the CS

falling edge after the SPI write (CLK_SEL[1:0] = 11), a

settling time is necessary before being able to reach

the internal oscillator nominal frequency. It is recom-

mended not to launch conversions before this nominal

clock frequency value has been established.

The opposite transition, from CLK_SEL[1:0] = 11 to

another clock mode, is described in Figure 6-16. This

transition is also not immediate in order to allow a

smooth transition from an SCK Output to an SCK Input

mode.

Writing the CLK_SEL[1:0] bits to ‘10’ or ‘0x’ resets the

internal master clock immediately, but the SCK is still

present as an output until CS sees a rising edge. After the

CS rising edge, the SCK output is placed in a

High-Impedance mode and the SCK becomes an output.

The master clock stays in Reset until the next CS falling

edge is detected. As soon as this happens, the SCK

can be used in the new selected mode.

FIGURE 6-15:

MCP3465R Transition from CLK_SEL[1:0] = 0x/10 to ‘11’.

Don’t Care

SDI

SDO

High-Z

Write CLK_MODE =

(Int with RC CLK output on pin

SCK)

MCLK

SCK

Internal MCLK mode (output on SCK) Validated

Reset MCLK

Start the Int OSC

TCLZ

Control Byte

Status Byte

IF CLK_MODE =

MCLK = SCK

IF CLK_MODE =

10 MCLK = Int RC OSC

Control Byte

Continuous

Clocking

Continuous Write

High-Z

Free-Running SCK Coming from Internal OSC

Input

SCK PAD

Direction

Output

High-Z

SPI Mode 1,1

SPI Mode 0,0

CS High Aborts SPI

Communication but doesn’t

Stop Internal MCLK

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