MCP3465R datasheet(64/110 Pages) MICROCHIP

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MCP3465R

DS20006414C-page 64

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6.2.1

COMMAND BYTE STRUCTURE

The COMMAND byte fully defines the command that

will be executed by the part. This byte is divided into

three parts: the device address bits (CMD[7:6]), the

command

address

bits

(CMD[5:2])

and

the

command-type bits (CMD[1:0]). See Table 6-1.

6.2.2

DEVICE ADDRESS BITS (CMD[7:6])

The SPI interface of the MCP3465R device is

addressable, which means that multiple devices can

communicate on the same SPI bus with only one Chip

Select line for all devices. Each device communication

starts by a CS falling edge, followed by the clocking of the

device address (CMD[7:6]). Each device contains an

internal device address which the device can respond to.

This address is coded on two bits, so four possible

addresses are available. The device address is

hard-coded within the device and should be deter-

mined when ordering the device. The device address is

part of the device markings to avoid potential confusion

(see Section 9.1 “Package Marking Information(*)”).

When the CMD[7:6] bits match the device address, the

communication will proceed and the part will execute

the commands defined in the control byte and its

subsequent data bytes.

When the CMD[7:6] bits do not correspond to the

address hard-coded in the device, the command is

ignored. In this case, the SDO output will become

high-impedance, which prevents bus contention errors

when multiple devices are connected on the same SPI

bus (see Figure 6-2). The user has to exit from this

communication through a CS rising edge to be able to

launch another command.

6.2.3

COMMAND ADDRESS BITS

(CMD[5:2])

The COMMAND byte contains four address bits

(CMD[5:2]) that can serve two purposes. In case of a

case of a Fast command, they determine which Fast

command is executed by the device.

In case of a Write command on a read-only register, the

command is not executed and the communication

should be aborted (CS rising edge) to place another

command. All registers can be read; there is no

undefined address in the register map.

6.2.4

COMMAND-TYPE BITS (CMD[1:0])

The last two bits of the COMMAND register byte define

the command type. These bits are an extension of the

typical read/write bits present in most SPI communica-

tion protocols. The two bits define four possible

command types: Incremental Write, Incremental Read,

Static Read and Fast command. Changing the com-

mand type within the same communication (while CS is

logic low) is not possible. The communication has to be

stopped (CS rising edge) and restarted (CS falling

edge) to change its command type. The list of possible

commands, their type and their possible command

addresses are described in Table 6-2.

TABLE 6-1:

COMMAND BYTE

CMD[7] CMD[6] CMD[5] CMD[4] CMD[3] CMD[2] CMD[1] CMD[0]

Device Address

Bits

Command Type

Bits

TABLE 6-2:

COMMAND TYPES

CMD[5:2]

CMD[1:0]

Command Description

0xxx

Don’t Care

100x

Don’t Care

1010

ADC Conversion Start/Restart Fast Command (overwrites ADC_MODE[1:0] = 11)

1011

ADC Standby Mode Fast Command (overwrites ADC_MODE[1:0] = 10)

1100

ADC Shutdown Mode Fast Command (overwrites ADC_MODE[1:0] = 00)

1101

Full Shutdown Mode Fast Command (overwrites CONFIG0[7:0] = 0x00 and

places the part in Full Shutdown mode)

1110

Device Full Reset Fast Command (resets the entire register map to default value)

1111

Don’t Care

ADDR

Static Read of Register Address, ADDR

ADDR

Incremental Write Starting at Register Address, ADDR

ADDR

Incremental Read Starting at Register Address, ADDR

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