MCP3465R datasheet(29/110 Pages) MICROCHIP

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DS20006414C-page 29

MCP3465R

When

running

conversions,

SCK

has

continuously clocking at a constant frequency to

ensure proper ADC accuracy. In this case, communica-

tions using the SPI interface should be synchronized

on the free-running clock and can be framed with a

proper usage of the CS pin.

When CLK_SEL[1:0] = 10, the MCLK is running based

on the internal oscillator and is not attached to the SCK

pin. In this case, SCK and MCLK are asynchronous

and the SCK pin is used only for the SPI interface

communications.

When CLK_SEL[1:0] = 11, the SCK pin becomes an

output for the internal oscillator and sends a

free-running clock at the AMCLK frequency. In this

case, the SCK pin is still working as the SCK input for

SPI communications.

The MCP3465R becomes the host device for the SCK

clock. The SPI communications have to be framed

using this free-running clock as the time base in order

to be correctly interpreted by the device.

3.3.3

SERIAL DATA OUTPUT PIN (SDO)

This pin is used for the SPI Data Output (SDO). The

SDO data are clocked out on the falling edge of SCK.

This pin stays high-impedance under the following

conditions:

• When CS pin is logic high.

• During the entire SPI write or Fast command

communication period after the SPI COMMAND

byte has been transmitted.

• After the two device address bits in the command

are transmitted, if the device address in the com-

mand does not match the internal chip device

address.

3.3.4

SERIAL DATA INPUT PIN (SDI)

This is the SPI Data Input (SDI) pin and it uses a

Schmitt Trigger structure. When CS is logic low, this

pin is used to send a COMMAND byte just after the CS

falling edge, which can be followed by data words of

various lengths. Data are clocked into the device on

the rising edge of SCK. Toggling SDI while reading a

3.4

Digital Ground (DGND)

DGND is the ground connection to internal digital

circuitry. To ensure accuracy and noise cancellation,

DGND must be connected to the same ground as

AGND, preferably with a star connection. If a digital

ground plane is available, it is recommended to tie this

pin to the plane of the Printed Circuit Board (PCB).

This plane should also reference all other digital

circuitry in the system. DGND is not internally connected

to AGND and must be connected externally.

3.5

Digital Power Supply (DVDD)

DVDD is the power supply pin for the digital circuitry

within the device. The voltage on this pin must be

maintained in the range specified by the Electrical

Characteristics table. For optimal performance, it is

recommended to connect appropriate bypass capaci-

tors (typically, a 10 µF ceramic in parallel with a 0.1 µF

ceramic). DVDD is monitored by the DVDD POR

monitoring circuit for the digital section.

3.6

Analog Power Supply (AVDD)

AVDD is the power supply pin for the analog circuitry

within the device. The voltage on this pin must be

maintained in the range specified by the Electrical

Characteristics table. For optimal performance, it is

recommended to connect appropriate bypass capaci-

tors (typically, a 10 µF ceramic in parallel with a 0.1 µF

ceramic). AVDD is monitored by the AVDD POR

monitoring circuit for the analog section.

3.7

Analog Ground (AGND)

AGND is the ground connection to internal analog

circuitry. To ensure accuracy and noise cancellation,

this pin must be connected to the same ground as

DGND, preferably with a star connection. If an analog

ground plane is available, it is recommended to tie this

pin to the plane of the PCB. This plane should also ref-

erence all other analog circuitry in the system. AGND is

the biasing voltage for the substrate of the die and is

not internally connected to DGND.

3.8

Exposed Pad (EP)

The pad is internally connected to AGND. It must be

connected to the analog ground of the PCB for optimal

accuracy and thermal performance. This pad can also

be left floating if necessary.

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