MCP3465R datasheet(72/110 Pages) MICROCHIP

72 / 110 page

MCP3465R

DS20006414C-page 72

 2020-2021 Microchip Technology Inc.

If the COMMAND byte defines a static read of the

ADCDATA register (address: 0x0), the ADC data will be

present on SDO and will be updated continuously at

each read. In this case, when a data ready interrupt

occurs within a read, the data are not corrupted and will

be updated to a new value after the old value has been

completely read. The ADC register contains a double

buffer that prevents data from being corrupted while

reading them. The part is able to stream output data

continuously with no additional command if the com-

munication is not stopped with a CS rising edge.

Figure 6-9 represents the continuous streaming of

incoming ADCDATA through the SPI port with both SPI

Modes 0,0 and 1,1.

For continuous reading of ADCDATA in SPI Mode 0,0,

once the data have been completely read after a Data

Ready Event, the SDO pin takes the MSb value of the

previous data at the end of the reading (falling edge of

the last SCK clock). If SCK stays Idle at logic low (by

definition of Mode 0,0), the SDO pin is updated at the

falling edge of the next Data Ready Event with the new

MSb of the data. This mechanism allows the device to

continuously read ADC data outputs seamlessly, even

in SPI Mode 0,0.

In SPI Mode 1,1, the SDO pin stays in the last state

(LSb of previous data) after a complete reading, which

also allows seamless Continuous Read mode.

The ADC output data can only be properly read after a

tDODR time, after the data ready interrupt comes in the

IRQ register. The tDODR timing is shorter than the time

necessary to input a command on the SDI pin, which

ensures proper reading when a new Read command is

triggered by the data ready interrupt. In case of contin-

uous reading (with CS pin kept logic low), the tDODR

timing must be carefully handled by the MCU, but the

interrupt service time is generally much longer than the

tDODR timing. Retrieving a Data Ready Event by read-

ing the STATUS byte or reading the IRQ register

automatically ensures that the tDODR timing is

respected.

FIGURE 6-9:

Continuous ADC Read (Data Streaming) with SPI Mode 0,0 and 1,1.

Don’t care

SPI mode 0,0; ADC Data Format : 32-bit

Don’t care

SCK

SDI

SDO

DATA0[31]

Hi-Z

Device latches SDI on rising edge

Device latches SDO on falling edge

Don’t care

Hi-Z

Device latches SDI on rising edge

Device latches SDO on falling edge

R/W

Don’t care

SCK

SDI

SDO

Don’t care

SCK

SDI

SDO

Data Ready Event

DATA1[31]

DATA0[31]

SDO changes synchronously with the falling

edge (DR interrupt flag)

only when MSB is present on SDO

DR Interrupt

(DATA1 is ready)

DATA0[0]

SPI mode 1,1; ADC Data Format : 32-bit

Data Ready Event

Read Start

DR Interrupt

(DATA1 is ready)

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