MCP3465R datasheet(73/110 Pages) MICROCHIP

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DS20006414C-page 73

MCP3465R

Continuous streaming is possible, but needs extra care

from the user to correctly synchronize with the device

by using the Data Ready Event.

When MCLK is generated externally, the user can

count the number of MCLK clocks sent to the device

and read the ADC data after the Data Ready Event that

is generated after a defined number of clock periods

(see Table 5-6 for more information about the number

of clocks required for obtaining Data Ready Events).

If the user desires to perform continuous streaming of

ADC output data, it is recommended to poll the STATUS

byte and start reading ADC data only when the

DR_STATUS bit is effectively set to ‘0’ (see Section 6.8.1

“Conversion Data Ready (DR) Interrupt” for more infor-

mation about the interrupt mechanisms attached to the

Data Ready Event).

Retrieving a data ready interrupt, by reading the

STATUS byte or reading the IRQ register, automatically

ensures that the tDODR timing is respected.

6.5

Securing Read Communications

through CRC-16 Checksum

Since some applications can generate or receive large

EMI/EMC interferences and large transient spikes, it is

helpful to secure SPI communications as much as

possible to maintain data integrity and desired

configurations during the application’s lifetime.

The communication data on the SDO pin can be

secured through the insertion of a Cyclic Redundancy

Check (CRC) checksum at the end of each read

sequence. The CRC checksum on communications

can be enabled or disabled through the EN_CRCCOM

bit in the CONFIG3 register. The CRC message

ensures the integrity of the read sequence bits

transmitted on the SDO pin.

The CRC checksum in the MCP3465R uses the 16-bit

CRC-16 ANSI polynomial, as defined in the IEEE 802.3

Standard: x16 +x15 +x2 +1.

This polynomial can also be noted as 0x8005. CRC-16

detects all single and double-bit errors, all errors with

an odd number of bits, all burst errors of 16 bits in

length or less and most errors for longer bursts. This

allows an excellent coverage of the SPI communication

errors that can occur in the system and heavily reduces

the risk of a miscommunication, even under noisy

environments.

When enabled, the CRC checksum (CRCCOM[15:0])

is propagated on SDO after each read communication

sequence.

In case of a Static Read command, the checksum is

propagated after each register read. In case of an

Incremental Read command, the checksum is propa-

gated after the last register read in the register map

(address: 0xF). Figure 6-11 and Figure 6-12 show

typical read communications in Static Read and

Incremental Read modes, respectively, when the

EN_CRCCOM bit is enabled. Since the STATUS byte

is propagated on SDO, it is part of the first message

and it is included in the calculation of the first check-

sum. For subsequent checksum calculations, the

message only contains the registers that are effectively

read in between two checksums.

The CRC-16 format displayed on the SDO pin depends

on the CRC_FORMAT bit in the CONFIG3 register (see

Figure 6-10). It can have a 16-bit or 32-bit format to be

compatible with both 16-bit and 32-bit MCUs. The

CRCCOM[15:0] bits calculated by the device do not

depend on the format (the device always calculates a

16-bit only CRC checksum).

FIGURE 6-10:

CRC Format Table for Read

Communications.

The CRC calculation computed by the device is fully

compatible with the CRC hardware contained in the

Direct Memory Access (DMA) of the PIC24 and PIC32

MCU product lines. The CRC message that should be

considered in the PIC® device DMA is the concatena-

tion of the read sequence and its associated

checksum. When the DMA CRC hardware computes

this extended message, the resulting checksum should

be 0x0000. Any other result indicates that a

miscommunication has occurred, and that the current

communication sequence should be stopped and

restarted.

CRCCOM[15:0]

0x0000

CRC_FORMAT = 0: 16-Bit

(Default)

CRC_FORMAT = 1: 32-Bit

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