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FXPS7115D4 датащи(PDF) 52 Page - NXP Semiconductors |
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FXPS7115D4 датащи(HTML) 52 Page - NXP Semiconductors |
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52 / 75 page ![]() NXP Semiconductors FXPS7115D4 Digital absolute pressure sensor, 40 kPa to 115 kPa Bit 7 6 5 4 3 2 1 0 Symbol ASICWFR_X[7:0] Reset N/A N/A N/A N/A N/A N/A N/A N/A Access R R R R R R R R Table 97. ASICWFR_X Register (address CCh) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ASICWFR_Y[7:0] Reset N/A N/A N/A N/A N/A N/A N/A N/A Access R R R R R R R R Table 98. ASICWFR_Y Register (address CDh) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ASICWLOT_L[7:0] Reset N/A N/A N/A N/A N/A N/A N/A N/A Access R R R R R R R R Table 99. ASICWLOT_L Register (address D0h) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ASICWLOT_H[7:0] Reset N/A N/A N/A N/A N/A N/A N/A N/A Access R R R R R R R R Table 100. ASICWLOT_H Register (address D1h) bit allocation 7.7.28 USERDATA_0 to USERDATA_E - user data registers User data registers are user programmable OTP registers that contain user-specific information. These registers are included in the user programmed OTP array error detection. These registers are readable and writable in SPI mode or I2C mode when ENDINIT is not set. 7.7.29 USERDATA_10 to USERDATA_1E - user data registers User data registers are user programmable OTP registers that contain user-specific information. These registers are included in the user programmed OTP array error detection. These registers are readable and writable in SPI mode or I2C mode when ENDINIT is not set. 7.7.30 Lock and CRC Registers The lock and CRC Registers are automatically programmed OTP registers that include the lock bit, the block identifier, and the block OTP array CRC use for error detection. These registers are automatically programmed when the corresponding data array is programmed to OTP using the Write OTP Enable register. FXPS7115D4 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2022. All rights reserved. Product data sheet Rev. 6 — 6 June 2022 52 / 75 |
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