 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
FXPS7115D4 датащи(PDF) 43 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
FXPS7115D4 датащи(HTML) 43 Page - NXP Semiconductors |
|
|
43 / 75 page  NXP Semiconductors FXPS7115D4 Digital absolute pressure sensor, 40 kPa to 115 kPa DATATYPE0[1] DATATYPE0[0] SNSDATA register contents 0 1 Absolute pressure (PABS) 1 1 Temperature Table 67. DATATYPE0[1:0] 7.7.11.3.2 DSP data type 1 selection bits (DATATYPE1) The DSP data type 1 selection bits select the type of data to be included in the SNSDATA1_L and SNSDATA1_H registers. DATATYPE1[1] DATATYPE1[0] SNSDATA register contents 0 1 Absolute pressure (PABS) 1 1 Temperature Table 68. DATATYPE1[1:0] 7.7.11.4 DSP_CFG_U4 - DSP user configuration #4 register (address 43h) The DSP user configuration register #4 is a user programmable read/write register that contains DSP-specific configuration information. This register is included in the read/write array error detection. Bit 7 6 5 4 3 2 1 0 Symbol reserved reserved reserved reserved reserved INT_OUT reserved reserved Reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 69. DSP_CFG_U4 - DSP user configuration #4 register (address 43h) bit allocation Bit Symbol Description 2 INT_OUT The interrupt pin configuration bit selects the mode of operation for the interrupt pin. 0 — Open drain, active high with pull-down current 1 — Open drain, active low with pullup current Table 70. DSP_CFG_U4 - DSP user configuration #4 register (address 43h) bit description 7.7.11.5 DSP_CFG_U5 - DSP user configuration #5 register (address 44h) The DSP user configuration register #5 is a read/write register that contains DSP-specific configuration information. This register is included in the read/write array error detection. Bit 7 6 5 4 3 2 1 0 Symbol ST_CTRL[3:0] reserved Factory default 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 71. DSP_CFG_U5 - DSP user configuration #5 register (address 44h) bit allocation Bit Symbol Description 7 to 4 ST_CTRL[3:0] The self-test control bits select one of the various analog and digital self-test features of the device as shown in Table 73. The self-test control bits are not included in the read/write array error detection. 3 to 0 reserved These bits are reserved. Table 72. DSP_CFG_U5 - DSP user configuration #5 register (address 44h) bit description FXPS7115D4 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2022. All rights reserved. Product data sheet Rev. 6 — 6 June 2022 43 / 75 |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
