MFS5600AMBA0ES datasheet(55/111 Pages) NXP

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NXP Semiconductors

FS5600

Automotive buck regulator and controller with voltage monitors and watchdog timer

17.13.1 Shut-down mode

This is the state of the FS5600 when a valid VIN is applied, but EN1 and EN2 pins are

held low.

From one of the operation modes, (INIT_RUN/NORMAL STATE/On Demand ABIST,

Deep Fail-Safe), when EN1 and EN2 = 0, the IC enters the shut-down mode through the

'Power Down' state.

When entering the shut-down mode from INIT_RUN, NORMAL STATE or on-demand

ABIST states, the FS5600 sequences the GPOs in the reverse order of the power-up at

the appropriate time. See Section 17.13.8 for details.

For example, if OTP_GPO1_DELAY is set to 1 ms, and OTP_GPO2_DELAY is set to 5

ms:

• When EN1 = EN2 = 0, GPO2 is asserted low immediately, 4 ms after which GPO1 is

asserted low, 1 ms after which SW1 and SW2 regulators are disabled.

• FS0B is asserted low immediately after NORMAL STATE is exited.

17.13.2 Built-in self-test (BIST)

Analog Built-in self-test (ABIST) and logical built-in self-test (LBIST) are executed in this

state if enabled. This state is bypassed if both are disabled.

17.13.3 Power-up

SW1, SW2, and the various GPOs in FS5600 are powered up in this state. SW1 and

SW2 are enabled after exiting BIST or thermal shutdown and if their respective ENx

pin is held high. The power-up state exits upon completion of the highest delay among

OTP_GPO1_DELAY[2:0], OTP_GPO2_DELAY[2:0] and OTP_GPO3_DELAY[2:0].

The OTP_PGOOD1_DELAY[2:0] and OTP_PGOOD2_DELAY[2:0] timers run in parallel

to the GPO timers and do not need to expire to exit the power-up state. PGOOD1 and

PGOOD2 may be released high even in the INIT_RUN state.

17.13.4 Power-up in Debug Mode

The FS5600 offers a Debug Mode of operation that is useful during system bring up and/

or development. When in Debug Mode, the following restrictions are in place:

• Deep Fail-Safe transition is disabled

• Watchdog window duration is set to infinite

To power up in Debug Mode, apply VDDOTP_GPIO1 = 8 V before EN1 or EN2 go high

or before VIN is applied. In this condition, the FS5600 pauses power-up and waits for

VDDOTP_GPIO1 < 1 V before continuing to power up in Debug Mode. Ensure that there

is board-level isolation on the VDDOTP_GPIO1 bus if the GPIO1 function is used at a

lower voltage level.

While VDDOTP_GPIO1 is maintained at 8 V, the following I2C commands can be sent to

open access to the OTP mirror registers:

SET_REG:FS5600:Functional:TM_ENTRY:0xD5A7

SET_REG:FS5600:Functional:TM_ENTRY:0xB8EE

SET_REG:FS5600:Functional:TM_ENTRY:0x0F37

FS5600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 2 August 2022

55 / 111

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